HDLBits从零开始——第111题到120题答案

目录

第111题：3-bit LFSR

第112题：32-bit LFSR

第113题：Shift register

第114题：Shift register

第115题：3-input LUT

第116题：Rule 90

第117题：Rule 110

第118题：Conway's Game of Life16x16

第119题：Simple FSM 1(asynchronous reset)

第120题：Simple FSM 1(synchronous reset)

---

第111题：3-bit LFSR

module top_module 
(
	input  [2:0] SW  ,    // R
	input  [1:0] KEY ,    // L and clk
	output [2:0] LEDR     // Q
);  

always@(posedge KEY[0])
    LEDR <= KEY[1] ? SW : {LEDR[1]^LEDR[2],LEDR[0],LEDR[2]};

endmodule

第112题：32-bit LFSR

module top_module
(
    input           clk     ,
    input           reset   ,    // Active-high synchronous reset to 32'h1
    output [31:0]   q
); 

always@(posedge clk)
    if(reset)
        q <= 32'h1;
    else
        q <= {0^q[0],q[31:23],q[22]^q[0],q[21:3],q[2]^q[0],q[1]^q[0]};

endmodule

第113题：Shift register

module top_module 
(
    input       clk     ,
    input       resetn  ,   // synchronous reset
    input       in      ,
    output      out
);

reg [2:0] reg_in;

always@(posedge clk)
    if(!resetn)
        {reg_in,out} <= 0;
    else
        {reg_in,out} <= {in,reg_in[2:0]};

endmodule

第114题：Shift register

module top_module 
(
    input  [3:0] SW  ,
    input  [3:0] KEY ,
    output [3:0] LEDR
);  

generate
    genvar i;
    for(i= 0;i< 3;i=i+ 1)
        begin:muxdff3_inst
            MUXDFF MUXDFF_insti
            (.clk(KEY[0]),.w(LEDR[i+1]),.R(SW[i]),.E(KEY[1]),.L(KEY[2]),.Q(LEDR[i])); 
        end
endgenerate

MUXDFF MUXDFF_inst4
(.clk(KEY[0]),.w(KEY[3]),.R(SW[3]),.E(KEY[1]),.L(KEY[2]),.Q(LEDR[3]));

endmodule

module MUXDFF 
(
    input   clk,
    input   w, R, E, L,
    output  Q
);
 
always@(posedge clk)
    Q <= L ? R : (E ? w : Q);
 
endmodule

第115题：3-input LUT

module top_module 
(
    input       clk     ,
    input       enable  ,
    input       S       ,
    input       A, B, C,
    output      Z 
); 

reg [7:0]   Q;

always@(posedge clk)
    if(enable)
        Q <= {Q,S};

assign  Z = Q[{A,B,C}];
    
endmodule

第116题：Rule 90

module top_module
(
    input           clk ,
    input           load,
    input   [511:0] data,
    output  [511:0] q 
); 

always@(posedge clk)
    if(load)
        q <= data;
    else
        q <= (q >> 1)^(q << 1);

endmodule

第117题：Rule 110

module top_module
(
    input           clk ,
    input           load,
    input   [511:0] data,
    output  [511:0] q 
); 

always@(posedge clk)
    if(load)
        q <= data;
    else
        q <= ((~q)&(q<<1)) | (q&(~(q >> 1))) | ((~(q << 1))&q);

endmodule

第118题：Conway's Game of Life16x16

module top_module
(
    input           clk ,
    input           load,
    input   [255:0] data,
    output  [255:0] q 
); 

reg [3:0]   count;

always@(posedge clk)
    if(load == 1'b1)
        q <= data;
    else
        for(integer i=0;i<256;i=i+1)
            begin
                if(i == 0)                  
                    count = q[1]+q[16]+q[17]+q[15]+q[31]+q[240]+q[241]+q[255];
                else if(i == 15)            
                    count = q[14]+q[30]+q[31]+q[255]+q[254]+q[240]+q[0]+q[16];
                else if(i == 240)           
                    count = q[239]+q[224]+q[225]+q[255]+q[241]+q[15]+q[0]+q[1];
                else if(i == 255)           
                    count = q[238]+q[239]+q[224]+q[254]+q[240]+q[14]+q[15]+q[0];
                else if(i>0 && i<15)        
                    count = q[i-1]+q[i+1]+q[i+15]+q[i+16]+q[i+17]+q[i+239]+q[i+240]+q[i+241];
                else if(i>240 && i<255)     
                    count = q[i-1]+q[i+1]+q[i-15]+q[i-16]+q[i-17]+q[i-240]+q[i-241]+q[i-239];
                else if(i%16 == 0)          
                    count = q[i-16]+q[i-15]+q[i+1]+q[i+16]+q[i+17]+q[i-1]+q[i+15]+q[i+31];
                else if(i%16 == 15)         
                    count = q[i-16]+q[i-17]+q[i-31]+q[i-1]+q[i-15]+q[i+16]+q[i+15]+q[i+1];
                else                        
                    count = q[i-1]+q[i+1]+q[i-16]+q[i-15]+q[i-17]+q[i+16]+q[i+15]+q[i+17];
                
                if((count==0)||(count==1)||(count>=4))  
                    q[i] <= 1'b0;
                else if(count==3)                       
                    q[i] <= 1'b1;
            end

endmodule

第119题：Simple FSM 1(asynchronous reset)

module top_module
(
    input       clk     ,
    input       areset  ,    // Asynchronous reset to state B
    input       in      ,
    output      out
);

    parameter A=0, B=1; 
    reg state, next_state;

    always @(*) 
        begin
            if((state == A) && (in == 1))
                next_state = A;
            else if((state == A) && (in == 0))
                next_state = B;
            else if((state == B) && (in == 1))
                next_state = B;
            else if((state == B) && (in == 0))
                next_state = A;
        end

    always @(posedge clk or posedge areset) 
        begin    // This is a sequential always block
            if(areset)
                state <= B;
            else
                state <= next_state;
        end

    // Output logic
    assign out = (state == B);

endmodule

第120题：Simple FSM 1(synchronous reset)

module top_module(clk, reset, in, out);
    input       clk;
    input       reset;    // Synchronous reset to state B
    input       in;
    output      out;
    
    reg         out;

    // Fill in state name declarations

    reg present_state, next_state;

    parameter A=0, B=1;

    always @(*) 
        begin
            if((present_state == A) && (in == 1))
                next_state = A;
            else if((present_state == A) && (in == 0))
                next_state = B;
            else if((present_state == B) && (in == 1))
                next_state = B;
            else if((present_state == B) && (in == 0))
                next_state = A;
        end

    always @(posedge clk) 
        begin    // This is a sequential always block
            if(reset)
                present_state <= B;
            else
                present_state <= next_state;
        end

    // Output logic
    assign out = (present_state == B);

endmodule