HDLBits刷题之2.1.8----Verilog Language----Basics----7458 chip

8.7458 chip

Create a module with the same functionality as the 7458 chip. It has 10 inputs and 2 outputs. You may choose to use an assign statement to drive each of the output wires, or you may choose to declare (four) wires for use as intermediate signals, where each internal wire is driven by the output of one of the AND gates.

题目意思是根据以上图设计输入输出关系表达式，可以定义wire来表示绿色线部分，也可以直接跳过这个步骤，一气呵成，代码如下所示： 

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );

    assign p1y=(p1a&p1b&p1c)|(p1d&p1e&p1f);
    assign p2y=(p2a&p2b)|(p2c&p2d);

endmodule