HDLBits刷题之2.2.6----Verilog Language----Vectors----Vector concatenation operator

6.Vector concatenation operator

Given several input vectors, concatenate them together then split them up into several output vectors. There are six 5-bit input vectors: a, b, c, d, e, and f, for a total of 30 bits of input. There are four 8-bit output vectors: w, x, y, and z, for 32 bits of output. The output should be a concatenation of the input vectors followed by two 1 bits:

 根据题目的意思，可以将短的数据通过{}连接成一个长的数据，最后两位写入11，才能够使得长度相对应，代码如下所示：

module top_module (
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z );//

    assign {w,x,y,z} = {a,b,c,d,e,f,2'b11};

endmodule