HDLBits刷题之2.2.5----Verilog Language----Vectors----Four-input gates

5.Four-input gates

Build a combinational circuit with four inputs, in[3:0].There are 3 outputs:

• out_and: output of a 4-input AND gate.
• out_or: output of a 4-input OR gate.
• out_xor: output of a 4-input XOR gate.

题目意思是建立一个3位输入电路，让这3位的每一位与，或，异或起来。即若定义一个3位输入变量 input[2:0] a; 

则 out_and = a[2]&a[1]&a[0];后面的则为同理，代码如下所示： 

module top_module( 
    input [3:0] in,
    output out_and,
    output out_or,
    output out_xor
);
    //最浅显易懂的方法
	/*
    assign out_and = in[3]&in[2]&in[1]&in[0];
    assign out_or  = in[3]|in[2]|in[1]|in[0];
    assign out_xor = in[3]^in[2]^in[1]^in[0];
    */
    
    assign out_and =& in;
    assign out_or  =| in;
    assign out_xor =^ in;
    
endmodule

下面这种方法则等效与上面的方法。