东北大学2024春季数字逻辑实验二

最新推荐文章于 2024-07-21 23:58:44 发布

西戎530

最新推荐文章于 2024-07-21 23:58:44 发布

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分类专栏：数电实验文章标签： fpga开发

本文链接：https://blog.csdn.net/qq_75018027/article/details/139276610

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~~实验一是书上原题就不写了~~

verilog语言fgpa开发，vivado运行仿真（modelsim安装的时候电脑蓝屏了后来就没继续装了）

题目：

基础题：用Verilog设计一个带低有效控制端的一位全加器，再利用级联方法构成带低有效控制端的8位加法器。

一位全加器代码模块：

module full_adder(A,B,C,EI,S,Cout);         //一位全加器
    input A;
    input B;
    input C;
    input EI;
    output S;
    output Cout;
assign S = (EI== 1'b0) ? (C ^ A ^ B) : 1'bz;
assign Cout = (EI == 1'b0) ? ((A & B) | (A& C) | (B & C)) : 1'bz;
endmodule

级联成八位全加器代码模块：

module full_adder8_tb;              //八位全加器

reg [7:0] A, B;
reg EI;
reg C0;
wire [7:0] Sum;
wire C8;

 full_adder8 DUT (
    .A(A),
    .B(B),
    .C0(C0),
    .EI(EI),
    .Sum(Sum),
    .C8(C8)
);

initial begin
    A = 8'b00000000; B = 8'b00000000; EI = 1'b0; C0 = 1'b0;
    #10 A = 8'b00000000; B = 8'b00000001; EI = 1'b0; C0 = 1'b0;
    #10 A = 8'b00000000; B = 8'b00000010; EI = 1'b0; C0 = 1'b0;
    #10 A = 8'b00000000; B = 8'b00000100; EI = 1'b0; C0 = 1'b0;
    #10 A = 8'b00001101; B = 8'b00001010; EI = 1'b0; C0 = 1'b1;
    #10 A = 8'b00000010; B = 8'b00010010; EI = 1'b0; C0 = 1'b0;
    #10 A = 8'b11111111; B = 8'b11111111; EI = 1'b0; C0 = 1'b0;
    #10 A = 8'b00001000; B = 8'b01000011; EI = 1'b0; C0 = 1'b0;
    #10 A = 8'b00010000; B = 8'b10000000; EI = 1'b0; C0 = 1'b0;
    #10 A = 8'b00000000; B = 8'b00000000; EI = 1'b1; C0 = 1'b0;
    #10 A = 8'b00000001; B = 8'b00010000; EI = 1'b1; C0 = 1'b1;
    $stop;
endmodule

引脚文件：

set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVCMOS33} [get_ports {Sum[0]}]
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS33} [get_ports {Sum[1]}]
set_property -dict {PACKAGE_PIN A24 IOSTANDARD LVCMOS33} [get_ports {Sum[2]}]
set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS33} [get_ports {Sum[3]}]
set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS33} [get_ports {Sum[4]}]
set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS33} [get_ports {Sum[5]}]
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS33} [get_ports {Sum[6]}]
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS33} [get_ports {Sum[7]}]
set_property -dict {PACKAGE_PIN C23 IOSTANDARD LVCMOS33} [get_ports {C8}]

set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports {A[0]}]
set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {A[1]}]
set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {A[2]}]
set_property -dict {PACKAGE_PIN P1 IOSTANDARD LVCMOS33} [get_ports {A[3]}]
set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports {A[4]}]
set_property -dict {PACKAGE_PIN L5 IOSTANDARD LVCMOS33} [get_ports {A[5]}]
set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports {A[6]}]
set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports {A[7]}]
set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports {B[0]}]
set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS33} [get_ports {B[1]}]
set_property -dict {PACKAGE_PIN M7 IOSTANDARD LVCMOS33} [get_ports {B[2]}]
set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS33} [get_ports {B[3]}]
set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVCMOS33} [get_ports {B[4]}]
set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports {B[5]}]
set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports {B[6]}]
set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS33} [get_ports {B[7]}]

set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports {EI}]
set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {C0}]
//这里是xc7a200tfbg676_2芯片，下同

扩展题：（1）用Verilog设计带低有效控制端的4位并行进位加法器，再利用层次设计方法构成带低有效控制端的8位并行加法器。

（2）用Verilog设计加减运算器，通过控制端完成8位加法和8位减法的转换。

四位并行加法器代码：

module adder_4 (                       //四位并行加法器
    input [3:0] A,
    input [3:0] B,
    input Cin,
    output [3:0] S,
    output Cout,
    input E
);

wire [3:0] G, P;
wire [3:0] c;

assign G = A & B;
assign P = A ^ B;

assign c[0] = Cin;
assign S[0] = (E == 1'b0) ? (A[0] ^ B[0] ^ Cin) : 4'bz;

genvar i;
generate
    for (i = 1; i < 4; i = i + 1) begin : gen_loop
        assign c[i] = G[i-1] | (P[i] & c[i-1]);
        assign S[i] = (E == 1'b0) ? (A[i] ^ B[i] ^ c[i]) : 4'bz;
    end
endgenerate

assign Cout = (E == 1'b0) ? (G[3] | (P[3] & c[3])) : 1'bz;

endmodule

引脚文件：

set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVCMOS33} [get_ports S[0]]
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS33} [get_ports S[1]]
set_property -dict {PACKAGE_PIN A24 IOSTANDARD LVCMOS33} [get_ports S[2]]
set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS33} [get_ports S[3]]

set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS33} [get_ports Cout]

set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports A[0]]
set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports A[1]]
set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports A[2]]
set_property -dict {PACKAGE_PIN P1 IOSTANDARD LVCMOS33} [get_ports A[3]]

set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports B[0]]
set_property -dict {PACKAGE_PIN L5 IOSTANDARD LVCMOS33} [get_ports B[1]]
set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports B[2]]
set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports B[3]]

set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports E]
set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS33} [get_ports Cin]

层次设计八位加法器：

module adder_4 (                   //四位加法器
    input [3:0] A,
    input [3:0] B,
    input Cin,
    output [3:0] S,
    output Cout,
    input E
);

wire [3:0] G, P;
wire [3:0] c;

assign G = A & B;
assign P = A ^ B;

assign c[0] = Cin;
assign S[0] = (E == 1'b0) ? (A[0] ^ B[0] ^ Cin) : 4'bz;

genvar i;
generate
    for (i = 1; i < 4; i = i + 1) begin : gen_loop
        assign c[i] = G[i-1] | (P[i] & c[i-1]);
        assign S[i] = (E == 1'b0) ? (A[i] ^ B[i] ^ c[i]) : 4'bz;
    end
endgenerate

assign Cout = (E== 1'b0) ? (G[3] | (P[3] & c[3])) : 1'bz;

endmodule


module adder_48 (           //八位加法器
    input [7:0] A,
    input [7:0] B,
    input Cin,
    output [7:0] S,
    output Cout,
    input E
);

wire [3:0] S_l, S_h;
wire Cout_low;

adder_4 a1 (
    .A(A[3:0]),
    .B(B[3:0]),
    .Cin(Cin),
    .S(S_l),
    .Cout(Cout_low),
    .E(E)
);

adder_4 a2 (
    .A(A[7:4]),
    .B(B[7:4]),
    .Cin(Cout_low),
    .S(S_h),
    .Cout(Cout),
    .E(E)
);

assign S = {S_h, S_l};

endmodule

引脚文件：

set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVCMOS33} [get_ports S[0]]
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS33} [get_ports S[1]]
set_property -dict {PACKAGE_PIN A24 IOSTANDARD LVCMOS33} [get_ports S[2]]
set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS33} [get_ports S[3]]
set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS33} [get_ports S[4]]
set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS33} [get_ports S[5]]
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS33} [get_ports S[6]]
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS33} [get_ports S[7]]
set_property -dict {PACKAGE_PIN C23 IOSTANDARD LVCMOS33} [get_ports Cout]
set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports A[0]]
set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports A[1]]
set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports A[2]]
set_property -dict {PACKAGE_PIN P1 IOSTANDARD LVCMOS33} [get_ports A[3]]
set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports A[4]]
set_property -dict {PACKAGE_PIN L5 IOSTANDARD LVCMOS33} [get_ports A[5]]
set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports A[6]]
set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports A[7]]
set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports B[0]]
set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS33} [get_ports B[1]]
set_property -dict {PACKAGE_PIN M7 IOSTANDARD LVCMOS33} [get_ports B[2]]
set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS33} [get_ports B[3]]
set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVCMOS33} [get_ports B[4]]
set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports B[5]]
set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports B[6]]
set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS33} [get_ports B[7]]
set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports E]
set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports Cin]

加减器（带符号位）：

module AbbStract(
    input [7:0] A, 
    input [7:0] B, 
    input E,    
    output reg [9:0] result 
);

always @(*) begin
    if(E) begin
        
         if (A > B) begin
            result[9] = 0; // 符号位为正
            result[8:0] = A - B;
        end
        else begin
             result[9] = 1; // 符号位为负
             result[8:0] = B - A;//小数减大数时符号位为1，结果用对应绝对值原码表示
        end
    end
    else begin
        
         result[9] = 0; // 符号位为正
        result[8:0] = A + B;
    end
end

endmodule

引脚文件：

set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVCMOS33} [get_ports result[0]]
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS33} [get_ports result[1]]
set_property -dict {PACKAGE_PIN A24 IOSTANDARD LVCMOS33} [get_ports result[2]]
set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS33} [get_ports result[3]]
set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS33} [get_ports result[4]]
set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS33} [get_ports result[5]]
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS33} [get_ports result[6]]
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS33} [get_ports result[7]]
set_property -dict {PACKAGE_PIN C23 IOSTANDARD LVCMOS33} [get_ports result[8]]
set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS33} [get_ports result[9]]
set_property -dict {PACKAGE_PIN T2 IOSTANDARD LVCMOS33} [get_ports E]
set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports A[0]]
set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports A[1]]
set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports A[2]]
set_property -dict {PACKAGE_PIN P1 IOSTANDARD LVCMOS33} [get_ports A[3]]
set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports A[4]]
set_property -dict {PACKAGE_PIN L5 IOSTANDARD LVCMOS33} [get_ports A[5]]
set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports A[6]]
set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports A[7]]
set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports B[0]]
set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS33} [get_ports B[1]]
set_property -dict {PACKAGE_PIN M7 IOSTANDARD LVCMOS33} [get_ports B[2]]
set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS33} [get_ports B[3]]
set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVCMOS33} [get_ports B[4]]
set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports B[5]]
set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports B[6]]
set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS33} [get_ports B[7]]

引脚我会在专栏另一篇文章解释

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东北大学2024春季数字逻辑实验二

verilog语言fgpa开发，vivado运行仿真（modelsim安装的时候电脑蓝屏了后来就没继续装了）设计一个带低有效控制端的一位全加器，再利用级联方法构成带低有效控制端的。位并行进位加法器，再利用层次设计方法构成带低有效控制端的。设计加减运算器，通过控制端完成。设计带低有效控制端的。
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