XILINX-DDR4-自定义componet（x8）-之一

1、MIG生成模板

Part type

Part name

Rank

StackHeight

CA Mirror

Data mask

Address width

Row width

Column width

Bank width

Bank group width

CS width

CKE width

ODT width

CK width

Memory speed grade

Memory density

Component density

Memory device width

Memory component width

Data bits per strobe

IO Voltages

Data widths

Min period

Max period

tCKE

tFAW

tFAW_dlr

tMRD

tRAS

tRCD

tREFI

tRFC

tRFC_dlr

tRP

tRRD_S

tRRD_L

tRRD_dlr

tRTP

tWR

tWTR_S

tWTR_L

tXPR

tZQCS

tZQINIT

tCCD_3ds

cas latency

cas write latency

burst length

Components

DDR4_CUSTOM

1

1

0

1

17

15

10

2

1

1

1

1

1

107E

4Gb

4Gb

16

16

8

1.2V

8,16,24,32,40,48,56,64,72,80

1071

1600

5000 ps

30000 ps

0

8 tck

34000 ps

13920 ps

7800000 ps

260000 ps

0

13920 ps

5300 ps

6400 ps

0

7500 ps

15000 ps

2500 ps

7500 ps

270 ns

128 tck

1024 tck

0

13

12

8

UDIMMs

DDR4_CUSTOM1

2

1

1