四级流水线（用于高速并行转串行的输出）

module Controller(
			input 		clk,
			input		rst_n,
			input		En,
			input		Ld,
			input	[7:0]		Data,
			output	reg[31:0]	R0 ,
			output	reg Clr_P3_P0   ,
			output	reg Ld_P3_P0    ,
			output	reg Ld_R0
	);
	//独热码
localparam	S_IDLE = 6'b000001,
			S_3	   = 6'b000010,   //四级流水线
			S_2    = 6'b000100,
			S_1    = 6'b001000,   //8
			S_FULL = 6'b010000,   //16
			S_WAIT = 6'b100000;   //32
			
reg [5:0]  current_state,next_state;
always@(posedge clk,negedge rst_n)begin
	if(!rst_n)
		current_state <= S_IDLE;
	else
		current_state <= next_state;
end

always @(*)
begin
     begin
            Clr_P3_P0   = 1'b0;
            Ld_P3_P0    = 1'b0;
            Ld_R0       = 1'b0;
     end
     case(current_state)
     S_IDLE    : begin
                      if(En)
                      begin
                           next_state = S_3 ;
                           Ld_P3_P0   = 1'b1;
                      end
                      else 
                           next_state = S_IDLE;
                   end
     S_3	   : begin
                           next_state = S_2 ;
                           Ld_P3_P0   = 1'b1;
                 end
     S_2       : begin
                           next_state = S_1 ;  
                           Ld_P3_P0   = 1'b1;  
                 end
     S_1       : begin
                           next_state = S_FULL; 
                           Ld_P3_P0   = 1'b1; 
                 end
     S_FULL    : begin
                           if(Ld)  //开始就进入加载数据的状态
                           begin
                                   Ld_R0  	  =1'b1;
                                   if( En )
                                   begin
                                           next_state = S_3;  
                                           Ld_P3_P0   = 1'b1; 
                                   end         
                                   else
                                   begin
                                           next_state = S_IDLE;
                                           Clr_P3_P0  = 1'b1; 
                                   end
                            end
                            else
                                           next_state = S_WAIT;
                                 
                 end
     S_WAIT    : begin       //32
                         if(Ld)  
                         begin //开始就进入加载数据的状态 
                                  Ld_R0  = 1'b1;
                                  if(En)
                                  begin
                                         Ld_P3_P0   = 1'b1;
                                         next_state = S_3; 
                                  end
                                  else
                                  begin                      
                                        next_state = S_IDLE; 
                                        Clr_P3_P0  = 1'b1;   
                                  end
                          end        
                          else   
                          begin             
                                  next_state = S_WAIT; 
                          end       
                 end   
     endcase
end



reg [7:0]P3,P2,P1,P0;
	
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		P3<=8'h0;
		P2<=8'h0;
		P1<=8'h0;
		P0<=8'h0;
	end
	else if(Ld_P3_P0)begin
		P3<=Data;
		P2<=P3;
		P1<=P2;
		P0<=P1;
	end
	else if(Clr_P3_P0)begin
		P3<=8'h0;
		P2<=8'h0;
		P1<=8'h0;
		P0<=8'h0;
	end
end

always@(posedge clk,negedge rst_n)begin
	if(!rst_n)begin
		R0<=32'h0;
	end
	else if(Ld_R0)
		R0<={P3,P2,P1,P0};
end
endmodule

顶层：

module pipe4stage_top(
			input			clk,
			input			rst_n,
			input	[7:0]	data,
			input			En,
			input			Ld,
			output [31:0]	R0
);
	wire	Clr_P3_P0  ;
	wire	Ld_P3_P0   ;
	wire	Ld_R0      ;

//wire [7:0] Data;

	Controller
		u_Controller(
			.clk		(clk),
			.rst_n		(rst_n),
			.En			(En),
			.Ld			(Ld),
			.Data       (data     )     ,
			.R0         (R0       )     ,

			.Clr_P3_P0	(Clr_P3_P0),
			.Ld_P3_P0	(Ld_P3_P0),
			.Ld_R0		(Ld_R0)
	);

	
endmodule

仿真：

module pipe4stage_tb;
	
	integer i;
	reg clk,rst_n;
	reg [7:0]data;
	reg En,Ld;
	wire [31:0]R0;
	
	parameter clk_cycle = 10;
	always #(clk_cycle/2) clk=~clk;
	initial begin
		clk=0;
		rst_n=0;
		data=0;
		En=0;
		Ld=0;
		
		
		#(2*clk_cycle)
		rst_n=1;
		#(2*clk_cycle)
		for(i=0;i<16;i=i+1)begin
			data = i;
			Ld =1 ;
			En =1;
			@(posedge clk);
		end
		En=0;
//		Ld=1;
		@(posedge clk)

		Ld=0;
		#(4*clk_cycle)
		$stop;
	end
	
	pipe4stage_top
		u_pipe4stage_top(
			.clk(clk),
			.rst_n(rst_n),
			.data(data),
			.En(En),
			.Ld(Ld),
			.R0(R0)
);
 
endmodule

仿真结果：