ALtera 设计注意事项-不断更新

(1)在设计中一定要将未定义的引脚配置为三态输入(As input tri-stated),由于Avalon内部默认低电平有效,所以,如果将引脚配置成输出并连接到地(As ouput drving groud),将会导致未使用的芯片的片选有效而长期占用总线,造成总线冲突。

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Designing with Low-Level Primitives Chapter 2. Primitive Reference Primitives ................................................................................................................................................ 2–1 ALT_INBUF ...................................................................................................................................... 2–1 ALT_OUTBUF .................................................................................................................................. 2–3 ALT_OUTBUF_TRI .......................................................................................................................... 2–6 ALT_IOBUF ....................................................................................................................................... 2–8 ALT_INBUF_DIFF ......................................................................................................................... 2–11 ALT_OUTBUF_DIFF ..................................................................................................................... 2–13 ALT_OUTBUF_TRI_DIFF ............................................................................................................. 2–14 ALT_IOBUF_DIFF .......................................................................................................................... 2–19 ALT_BIDIR_DIFF ........................................................................................................................... 2–22 ALT_BIDIR_BUF ............................................................................................................................ 2–25 LCELL .............................................................................................................................................. 2–27 DFF ................................................................................................................................................... 2–28 CARRY and CARRY_SUM ........................................................................................................... 2–29 CASCADE ....................................................................................................................................... 2–30 LUT_INPUT .................................................................................................................................... 2–31 LUT_OUTPUT ................................................................................................................................ 2–32
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