OpenRisc-58-ORPSoC调试环境的构建

引言

之前我们在PC上构建了ORPSoC的仿真环境，通过仿真环境，我们可以观察任何模块的工作波形，极大的方便了问题定位和错误分析。但是，“是骡子是马，拉出来溜溜”，只能看看仿真波形显然还不过瘾，我们还需要用FPGA板子跑一边才行。但要想在板子上运行和调试软件，最方便最直接的方式就是用gdb将程序load到内存，进行调试运行。本小节就以ML501板子为例来说明OpenRISC调试系统的构建过程。

 

1，  调试系统结构

 

其中棕色模块来自advanced debug system，PC端用的是orpsoc的vox的ubuntu镜像，蓝色模块来自ORPSoCv2 for ML501。

 

2，  资源准备

a,Ubuntu镜像

http://opencores.org/or1k/Ubuntu_VirtualBox-image_updates_and_information

b,adv_debug_sys

http://opencores.org/project,adv_debug_sys

c,ML501板子及下载器。

 http://www.xilinx.com/products/boards-and-kits/HW-V5-ML501-UNI-G.htm

3，  调试环境的构建

1>    安装adv_jtag_bridge

解压：

tar xvf adv_debug_sys_latest.tar.gz

安装：

cd adv_debug_sys/trunk/Software/adv_jtag_bridge
./autogen.sh
./configure
./make
./sudo make install

2>    在windows下构建ORPSOC针对ML501的ISE工程

ORPSOCv2的工程有两种方式，一种是在linux下，另外一种是在windows下。

linux下的工程，前面已经介绍过了：http://blog.csdn.net/rill_zhen/article/details/16880801

安装完ISE之后，就可以综合了。

下面介绍windows下的综合，

首先根据linux下的ise的prj文件，将对应的所有文件copy到windows下。

prj文件内容如下：

orpsoc.prj：

verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/arbiter/arbiter_bytebus.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/arbiter/arbiter_dbus.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/arbiter/arbiter_ibus.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/clkgen/clkgen.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/gpio/gpio.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/lfsr/lfsr.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/orpsoc_top/orpsoc_top.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/ddr2_chipscope.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/ddr2_ctrl.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/ddr2_idelay_ctrl.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/ddr2_infrastructure.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/ddr2_mem_if_top.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/ddr2_mig.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/ddr2_phy_calib.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/ddr2_phy_ctl_io.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/ddr2_phy_dm_iob.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/ddr2_phy_dq_iob.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/ddr2_phy_dqs_iob.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/ddr2_phy_init.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/ddr2_phy_io.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/ddr2_phy_top.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/ddr2_phy_write.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/ddr2_top.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/ddr2_usr_addr_fifo.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/ddr2_usr_rd.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/ddr2_usr_top.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/ddr2_usr_wr.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/xilinx_ddr2_if_cache.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ddr2/xilinx_ddr2.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../rtl/verilog/xilinx_ssram/xilinx_ssram.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../../../../rtl/verilog/cfi_ctrl/cfi_ctrl_engine.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../../../../rtl/verilog/cfi_ctrl/cfi_ctrl.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../../../../rtl/verilog/dbg_if/dbg_cpu_registers.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../../../../rtl/verilog/dbg_if/dbg_cpu.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../../../../rtl/verilog/dbg_if/dbg_crc32_d1.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../../../../rtl/verilog/dbg_if/dbg_if.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../../../../rtl/verilog/dbg_if/dbg_register.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../../../../rtl/verilog/dbg_if/dbg_wb.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../../../../rtl/verilog/ethmac/eth_clockgen.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../../../../rtl/verilog/ethmac/eth_crc.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../../../../rtl/verilog/ethmac/eth_fifo.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../../../../rtl/verilog/ethmac/eth_maccontrol.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../../../../rtl/verilog/ethmac/eth_macstatus.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../../../../rtl/verilog/ethmac/ethmac.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../../../../rtl/verilog/ethmac/eth_miim.v
verilog work /home/openrisc/soc-design/orpsocv2/boards/xilinx/ml501/syn/xst/run/../../../../../../rtl/verilog/ethmac/eth_outputcontrol.v
verilog work /home/openr