关于全局时钟引脚和局部时钟引脚以及BUFG和BUFR

Place:645 - A clock IOB clock component is not placed at an optimal clock IOB site. The clock IOB component <I_Ad9783_8_Dco_p> is placed at site <AY35>. The clock IO site can use the fast path between the IO and the Clock buffer/GCLK if the IOB is placed in the master Clock IOB Site. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule. < NET "I_Ad9783_8_Dco_p" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

在布局布线时遇到这个错误。我将一个差分时钟输入通过一个缓冲器IBUFGDS，但是，这个差分时钟不是通过GC进来的，而是通过CC进来的，因而不能通过BUFG，只能通过BUFR。

解决办法1：在约束文件中加入NET "I_Ad9783_8_Dco_p" CLOCK_DEDICATED_ROUTE = FALSE;

解决办法2：将此差分时钟先通过一个IBUFDS，再通过一个BUFR。

关于CLOCK_DEDICATED_ROUTE，指示软件是否遵循特定体系结构的时钟放置规则。

当CLOCK_DEDICATED_ROUTE没有使用或者值为TRUE时，，必须遵循时钟放置规则，否则就会如上报错。当CLOCK_DEDICATED_ROUTE值为FALSE时，，软件会忽略特定的时钟放置规则并继续布局布线。

当使用CLOCK_DEDICATED_ROUTE = FALSE时，可能会导致非常差的时序结果。所以推荐使用解决办法2。但如果时钟输入引脚即不是GC也不是CC，那就只能修改硬件或者使用CLOCK_DEDICATED_ROUTE = FALSE了。

加了CLOCK_DEDICATED_ROUTE = FALSE之后，就算你程序中加了BUFG，但布局布线之后还是没有BUFG的。

 

之后又发现了一个问题，我的输入时钟是320MHz的，但BUFR最大频率是250MHz的，因而只能选择其他办法了。可以通过一个DCM或PLL，再通过一个BUFG，再由BUFG连到全局时钟线上。