【TINY4412】U-BOOT移植笔记：（5）时钟分析

【TINY4412】U-BOOT移植笔记：（5）时钟分析

宿主机 ： 虚拟机 Ubuntu 16.04 LTS / X64
目标板[底板]： Tiny4412SDK - 1506
目标板[核心板]： Tiny4412 - 1412
U-BOOT版本： 2017.03
交叉编译器： gcc-arm-none-eabi-5_4-2016q3
日期： 2017-4-22 15:01:27
作者： SY

时钟配置

• 开发板启动方式

  1. 根据 Android_Exynos4412_iROM_Secure_Booting_Guide_Ver.1.00.00.pdf提供的方式：

  OM[5:1]	启动设备
  5b’00010	SDMMC_CH2
  5b’00100	eMMC44_CH4

  通过核心板原理图，可以看出，OM0 = 1; OM1 = 0，OM4 = 0， OM5 = 0;
  通过SD卡启动时，OM2 = 1； 通过eMMC启动时，OM3 = 1;
  开发板在XusbXTI引脚，连接一个24MHz的晶振，
  参考Exynos 4412 SCP_Users Manual_Ver.0.10.00_Preliminary0.pdf 的P455页，
  在最左边找到XusbXTI位置向上看,通过一个多路选择器输出到FINpll，而开关就是XOM[0]，
  我们知道XOM[0] = 1,因此芯片将使用XusbXTI作为系统时钟源。

• 时钟分析

详见P584(APLL_CON0)和P451(表格7-2)
要想达到：Fout = 1400MHz
MDIV = 175
PDIV = 3
SDIV = 0
Fin = 24MHz
根据公式：FOUT = MDIV * FIN / (PDIV * (2 ^ sdiv));
-> Fout = 175 * 24 / (3 * 1) = 1400MHz

/* 系统推荐频率 */
 freq (ARMCLK) = 1400 MHz at 1.3 V
 freq (ACLK_COREM0) = 350 MHz at 1.3V
 freq (ACLK_COREM1) = 188 MHz at 1.3 V
 freq (PERIPHCLK) = 1400 MHz at 1.3 V
 freq (ATCLK) = 214 MHz at 1.3 V
 freq (PCLK_DBG) = 107 MHz at 1.3 V
 freq (SCLK_DMC) = 400 MHz at 1.0 V
 freq (ACLK_DMCD) = 200 MHz at 1.0 V
 freq (ACLK_DMCP) = 100 MHz at 1.0 V
 freq (ACLK_ACP) = 200 MHz at 1.0 V
 freq (PCLK_ACP) = 100 MHz at 1.0 V
 freq (SCLK_C2C) = 400 MHz at 1.0 V
 freq (ACLK_C2C) = 200 MHz at 1.0 V
 freq (ACLK_GDL) = 200 MHz at 1.0 V
 freq (ACLK_GPL) = 100 MHz at 1.0 V
 freq (ACLK_GDR) = 200 MHz at 1.0 V
 freq (ACLK_GPR) = 100 MHz at 1.0 V
 freq (ACLK_400_MCUISP) = 400 MHz at 1.0 V
 freq (ACLK_200) = 160 MHz at 1.0 V
 freq (ACLK_100) = 100 MHz at 1.0 V
 freq (ACLK_160) = 160 MHz at 1.0 V
 freq (ACLK_133) = 133 MHz at 1.0 V
 freq (SCLK_ONENAND) = 160 MHz at 1.0 V

<< ------------------ CMU_CPU ------------------ >>
24MHz->经过APLL倍频后，升至1400MHz。与系统频率一致
-> DIVcore = 1 -> DIVcore2 = 1 -> ARMCLK = 1400MHz

CLK_DIV_CPU0寄存器：
1. ARMCLK = DOUTCORE/(CORE2_RATIO + 1);
  1400 = 1400 / (CORE2_RATIO + 1);
  -> CORE2_RATIO = 0;
2. SCLKAPLL = MOUTAPLL/(APLL_RATIO + 1);
  -> SCLKAPLL = 1400 / (1 + 1) = 700MHz;
  （疑问：为什么APLL_RATIO = 1 ？）
3. PCLK_DBG = ATCLK/(PCLK_DBG_RATIO + 1);
  107 = 214 / (PCLK_DBG_RATIO + 1);
  -> PCLK_DBG_RATIO = 1;
4. ATCLK = MOUTCORE/(ATB_RATIO + 1);
  214 = 1400 / (ATB_RATIO + 1);
  -> ATB_RATIO = 6;
5. PERIPHCLK = DOUTCORE/(PERIPH_RATIO + 1);
  1400 = 1400/(PERIPH_RATIO + 1);
  -> PERIPH_RATIO = 0;
6. ACLK_COREM1 = ARMCLK/(COREM1_RATIO +1);
  188 = 1400 / (COREM1_RATIO + 1)；
  -> COREM1_RATIO = 7;
7. ACLK_COREM0 = ARMCLK/(COREM0_RATIO +1);
  350 = 1400 / (COREM0_RATIO + 1);
  -> COREM0_RATIO = 3;
8. DIVCORE_OUT = MOUTCORE/(CORE_RATIO +1);
  -> DIVCORE_OUT = 1400 / 1 = 1400MHz

CLK_DIV_CPU1寄存器:
1. ACLK_CORES = ARMCLK/(CORES_RATIO + 1);
  233 = 1400 / (CORES_RATIO + 1);
  -> CORES_RATIO = 5;
2. SCLK_HPM = DOUTCOPY/(HPM_RATIO + 1);
  200 = 200 / (HPM_RATIO + 1);
  -> HPM_RATIO = 0;
3. DOUTCOPY = MOUTHPM/(COPY_RATIO + 1);
  200 = 1400 / (COPY_RATIO + 1);
  -> COPY_RATIO = 6;

<< ------------------ CMU_CPU ------------------ >>
CLK_DIV_DMC0寄存器：
1. ACLK_DMCP = ACLK_DMCD/(DMCP_RATIO + 1);
  100 = 200 / (DMCP_RATIO + 1);
  -> DMCP_RATIO = 1;
2. ACLK_DMCD = DOUTDMC/(DMCD_RATIO + 1);
  200 = 400 / (DMCD_RATIO + 1);
  -> DMCD_RATIO = 1;
3. DOUTDMC = MOUTDMC_BUS/(DMC_RATIO + 1);
  400 = 800 / (DMC_RATIO + 1);
  -> DMC_RATIO = 1;
4. SCLK_DPHY = MOUTDPHY/(DPHY_RATIO + 1);
  400 = 800 / (DPHY_RATIO + 1);
  -> DPHY_RATIO = 1;
5. PCLK_ACP = ACLK_ACP/(ACP_PCLK_RATIO + 1);
  100 = 200 / (ACP_PCLK_RATIO + 1);
  -> ACP_PCLK_RATIO = 1;
6. ACLK_ACP = MOUTDMC_BUS/(ACP_RATIO + 1);
  200 = 800 / (ACP_RATIO + 1);
  -> ACP_RATIO = 3;

CLK_DIV_DMC1寄存器：
1. ACLK_C2C = MOUTC2C_ACLK/(C2C_ACLK_RATIO + 1);
  200 = 400 / (C2C_ACLK_RATIO + 1);
  -> C2C_ACLK_RATIO = 1;
2. SCLK_PWI = MOUTPWI/(PWI_RATIO + 1);
  100 = 800 / (PWI_RATIO + 1);
  -> PWI_RATIO = 7;
3. SCLK_C2C = MOUTC2C / (C2C_RATIO + 1);
  400 = 800 / (C2C_RATIO + 1);
  -> C2C_RATIO = 1;
4. SCLK_G2D_ACP = MOUTG2D_ACP / (G2D_ACP_RATIO + 1);
  200 = 800 / (G2D_ACP_RATIO + 1);
  -> G2D_ACP_RATIO = 3;
5. IECDVSEMCLKEN = ACLK_DMCP/( DVSEM_RATIO+ 1);
  50 = 100 / ( DVSEM_RATIO+ 1);
  -> DVSEM_RATIO = 1;
6. IECDPMCLKEN = ACLK_DMCP/( DPM_RATIO+ 1);
  50 = 100 / ( DPM_RATIO + 1);
  -> DPM_RATIO = 1;

时钟这一块学起来比较难，而且配置不好会影响后面驱动的移植，因此，可以先跳过该章节！