tiny4412 基础（五）时钟体系（续）

在iROM里面有设置PLL：

本文描述使用uart使用iROM初始化的MPLL来反过来读关键寄存器的值

先看结果：

-----------------------src-------------------------
src_cpu      : 01000001
src_leftbus  : 00000001
src_rightbus : 00000001
src_top0     : 01110000
src_top1     : 00001000
src_peril0   : 00066666
src_peril1   : 01610055
-----------------------div-------------------------
div_cpu0     : 00773730
div_cpu1     : 00000077
div_top      : 00015470
div_peril0   : 00033333
div_peril1   : 09010907
div_peril2   : 00000907
div_peril3   : 000000F0
div_peril4   : 00000000
div_peril5   : 00000000
div_dmc0     : 00111713
div_dmc1     : 01011171
------------------------ctrl------------------------
apll_con0    : A0640301
apll_con1    : 00003800
mpll_con0    : A0640301
mpll_con1    : 00003800

首先，uart的初始化：

void uart_init(void)
{
    /* 1.设置相应的GPIO用于串口功能 */
    GPA0CON = 0x22222222;
    GPA1CON = 0x222222;

    /* 2.设置UART时钟源SCLK_UART */
    /* 2.1 CLK_SRC_DMC  : bit[12]即MUX_MPLL_SEL=1, SCLKMPLLL使用MPLL的输出
     * 2.2 CLK_SRC_TOP1 : bit[12]即MUX_MPLL_USER_SEL_T=1, MUXMPLL使用SCLKMPLLL
     * 2.3 CLK_SRC_PERIL0 : bit[3:0]即UART0_SEL=6, MOUTUART0使用SCLKMPLL_USER_T
     * 所以, MOUTUART0即等于MPLL的输出, 800MHz
     */
    /*
     *   PWM_SEL = 0;
     *   UART5_SEL = 0;
     *   UART4_SEL = 6;      // 串口时钟源选 SCLKMPLL_USER_T
     *   UART3_SEL = 6;
     *   UART2_SEL = 6;
     *   UART1_SEL = 6;
     *   UART0_SEL = 6;
     */
    CLK_SRC_PERIL0 = ((0 << 24) | (0 << 20) | (6 << 16) | (6 << 12) | (6<< 8) | (6 << 4)    | (6));

    /*
    * MUX_MPLL_USER_SEL_T = 1
    */
    CLK_SRC_TOP1 |= (0x1 << 12);

    CLK_DIV_PERIL0 = ((3 << 20) | (3 << 16) | (3 << 12) | (3 << 8) | (3 << 4) | (3));

    /* 3.设置串口0相关 */
    /* 设置FIFO中断触发阈值
     * 使能FIFO
     */
    UFCON0 = 0x111;
    
    /* 设置数据格式: 8n1, 即8个数据位,没有较验位,1个停止位 */
    ULCON0 = 0x3;
    
    /* 工作于中断/查询模式
     * 另一种是DMA模式,本章不使用
     */
    UCON0  = 0x5;
    
    /* SCLK_UART0=100MHz, 波特率设置为115200
     * 寄存器的值如下计算:
     *    DIV_VAL   = 100,000,000 / (115200 * 16)   - 1 = 53.25
     *    UBRDIVn0  = 整数部分 = 53
     *    UFRACVAL0 = 小数部分 x 16 = 0.25 * 16 = 4
     */
    UBRDIV0 = 53;
    UFRACVAL0 = 4;
}

为了方便实现printf来输出：
 

void putchar_hex(char c)
{
	char * hex = "0123456789ABCDEF";

	putc(hex[(c>>4) & 0x0F]);
	putc(hex[(c>>0) & 0x0F]);
}

void putint_hex(int a)
{
	putchar_hex( (a>>24) & 0xFF );
	putchar_hex( (a>>16) & 0xFF );
	putchar_hex( (a>>8) & 0xFF );
	putchar_hex( (a>>0) & 0xFF );
}

char * itoa(int a, char * buf)
{
	int num = a;
	int i = 0;
	int len = 0;

	do
	{
		buf[i++] = num % 10 + '0';
		num /= 10;
	}while (num);
	buf[i] = '\0';

	len = i;
	for (i = 0; i < len/2; i++)
	{
		char tmp;
		tmp = buf[i];
		buf[i] = buf[len-i-1];
		buf[len-i-1] = tmp;
	}
	
	return buf;
}


typedef int * va_list;
#define va_start(ap, A)		(ap = (int *)&(A) + 1)
#define va_arg(ap, T)		(*(T *)ap++)
#define va_end(ap)		((void)0)

int printf(const char * format, ...)
{
	char c;	
	va_list ap;
		
	va_start(ap, format);
	
	while ((c = *format++) != '\0')
	{
		switch (c)
		{
			case '%':
			c = *format++;
				
			switch (c)
			{
				char ch;
				char * p;
				int a;
				char buf[100];
									
				case 'c':
					ch = va_arg(ap, int);
					putc(ch);
					break;
				case 's':
					p = va_arg(ap, char *);
					puts(p);
					break;					
				case 'x':
					a = va_arg(ap, int);
					putint_hex(a);
						break;		
				case 'd':
					a = va_arg(ap, int);
					itoa(a, buf);
					puts(buf);
					break;	
					
				default:
					break;
			}				
			break;		
	
		default:
			putc(c);
			break;
		}
	}
	
	return 0;	
}

然后使用u-boot里面时钟相关头文件，

#define EXYNOS4X12_CLOCK_BASE		0x10030000


struct exynos4x12_clock {
	unsigned char	res1[0x4200];
	unsigned int	src_leftbus;
	unsigned char	res2[0x1fc];
	unsigned int	mux_stat_leftbus;
	unsigned char	res3[0xfc];
	unsigned int	div_leftbus;
	unsigned char	res4[0xfc];
	unsigned int	div_stat_leftbus;
	unsigned char	res5[0x1fc];
	unsigned int	gate_ip_leftbus;
	unsigned char	res6[0x12c];
	unsigned int	gate_ip_image;
	unsigned char	res7[0xcc];
	unsigned int	clkout_leftbus;
	unsigned int	clkout_leftbus_div_stat;
	unsigned char	res8[0x37f8];
	unsigned int	src_rightbus;
	unsigned char	res9[0x1fc];
	unsigned int	mux_stat_rightbus;
	unsigned char	res10[0xfc];
	unsigned int	div_rightbus;
	unsigned char	res11[0xfc];
	unsigned int	div_stat_rightbus;
	unsigned char	res12[0x1fc];
	unsigned int	gate_ip_rightbus;
	unsigned char	res13[0x15c];
	unsigned int	gate_ip_perir;
	unsigned char	res14[0x9c];
	unsigned int	clkout_rightbus;
	unsigned int	clkout_rightbus_div_stat;
	unsigned char	res15[0x3608];
	unsigned int	epll_lock;
	unsigned char	res16[0xc];
	unsigned int	vpll_lock;
	unsigned char	res17[0xec];
	unsigned int	epll_con0;
	unsigned int	epll_con1;
	unsigned int	epll_con2;
	unsigned char	res18[0x4];
	unsigned int	vpll_con0;
	unsigned int	vpll_con1;
	unsigned int	vpll_con2;
	unsigned char	res19[0xe4];
	unsigned int	src_top0;
	unsigned int	src_top1;
	unsigned char	res20[0x8];
	unsigned int	src_cam;
	unsigned int	src_tv;
	unsigned int	src_mfc;
	unsigned int	src_g3d;
	unsigned char	res21[0x4];
	unsigned int	src_lcd;
	unsigned int	src_isp;
	unsigned int	src_maudio;
	unsigned int	src_fsys;
	unsigned char	res22[0xc];
	unsigned int	src_peril0;
	unsigned int	src_peril1;
	unsigned int	src_cam1;
	unsigned char	res23[0xb4];
	unsigned int	src_mask_top;
	unsigned char	res24[0xc];
	unsigned int	src_mask_cam;
	unsigned int	src_mask_tv;
	unsigned char	res25[0xc];
	unsigned int	src_mask_lcd;
	unsigned int	src_mask_isp;
	unsigned int	src_mask_maudio;
	unsigned int	src_mask_fsys;
	unsigned char	res26[0xc];
	unsigned int	src_mask_peril0;
	unsigned int	src_mask_peril1;
	unsigned char	res27[0xb8];
	unsigned int	mux_stat_top0;
	unsigned int	mux_stat_top1;
	unsigned char	res28[0x10];
	unsigned int	mux_stat_mfc;
	unsigned int	mux_stat_g3d;
	unsigned char	res29[0x28];
	unsigned int	mux_stat_cam1;
	unsigned char	res30[0xb4];
	unsigned int	div_top;
	unsigned char	res31[0xc];
	unsigned int	div_cam;
	unsigned int	div_tv;
	unsigned int	div_mfc;
	unsigned int	div_g3d;
	unsigned char	res32[0x4];
	unsigned int	div_lcd;
	unsigned int	div_isp;
	unsigned int	div_maudio;
	unsigned int	div_fsys0;
	unsigned int	div_fsys1;
	unsigned int	div_fsys2;
	unsigned int	div_fsys3;
	unsigned int	div_peril0;
	unsigned int	div_peril1;
	unsigned int	div_peril2;
	unsigned int	div_peril3;
	unsigned int	div_peril4;
	unsigned int	div_peril5;
	unsigned int	div_cam1;
	unsigned char	res33[0x14];
	unsigned int	div2_ratio;
	unsigned char	res34[0x8c];
	unsigned int	div_stat_top;
	unsigned char	res35[0xc];
	unsigned int	div_stat_cam;
	unsigned int	div_stat_tv;
	unsigned int	div_stat_mfc;
	unsigned int	div_stat_g3d;
	unsigned char	res36[0x4];
	unsigned int	div_stat_lcd;
	unsigned int	div_stat_isp;
	unsigned int	div_stat_maudio;
	unsigned int	div_stat_fsys0;
	unsigned int	div_stat_fsys1;
	unsigned int	div_stat_fsys2;
	unsigned int	div_stat_fsys3;
	unsigned int	div_stat_peril0;
	unsigned int	div_stat_peril1;
	unsigned int	div_stat_peril2;
	unsigned int	div_stat_peril3;
	unsigned int	div_stat_peril4;
	unsigned int	div_stat_peril5;
	unsigned int	div_stat_cam1;
	unsigned char	res37[0x14];
	unsigned int	div2_stat;
	unsigned char	res38[0x29c];
	unsigned int	gate_ip_cam;
	unsigned int	gate_ip_tv;
	unsigned int	gate_ip_mfc;
	unsigned int	gate_ip_g3d;
	unsigned char	res39[0x4];
	unsigned int	gate_ip_lcd;
	unsigned int	gate_ip_isp;
	unsigned char	res40[0x4];
	unsigned int	gate_ip_fsys;
	unsigned char	res41[0x8];
	unsigned int	gate_ip_gps;
	unsigned int	gate_ip_peril;
	unsigned char	res42[0xc];
	unsigned char	res43[0x4];
	unsigned char	res44[0xc];
	unsigned int	gate_block;
	unsigned char	res45[0x8c];
	unsigned int	clkout_cmu_top;
	unsigned int	clkout_cmu_top_div_stat;
	unsigned char	res46[0x3600];
	unsigned int	mpll_lock;
	unsigned char	res47[0xfc];
	unsigned int	mpll_con0;
	unsigned int	mpll_con1;
	unsigned char	res48[0xf0];
	unsigned int	src_dmc;
	unsigned char	res49[0xfc];
	unsigned int	src_mask_dmc;
	unsigned char	res50[0xfc];
	unsigned int	mux_stat_dmc;
	unsigned char	res51[0xfc];
	unsigned int	div_dmc0;
	unsigned int	div_dmc1;
	unsigned char	res52[0xf8];
	unsigned int	div_stat_dmc0;
	unsigned int	div_stat_dmc1;
	unsigned char	res53[0xf8];
	unsigned int	gate_bus_dmc0;
	unsigned int	gate_bus_dmc1;
	unsigned char	res54[0x1f8];
	unsigned int	gate_ip_dmc0;
	unsigned int	gate_ip_dmc1;
	unsigned char	res55[0xf8];
	unsigned int	clkout_cmu_dmc;
	unsigned int	clkout_cmu_dmc_div_stat;
	unsigned char	res56[0x5f8];
	unsigned int	dcgidx_map0;
	unsigned int	dcgidx_map1;
	unsigned int	dcgidx_map2;
	unsigned char	res57[0x14];
	unsigned int	dcgperf_map0;
	unsigned int	dcgperf_map1;
	unsigned char	res58[0x18];
	unsigned int	dvcidx_map;
	unsigned char	res59[0x1c];
	unsigned int	freq_cpu;
	unsigned int	freq_dpm;
	unsigned char	res60[0x18];
	unsigned int	dvsemclk_en;
	unsigned int	maxperf;
	unsigned char	res61[0x8];
	unsigned int	dmc_freq_ctrl;
	unsigned int	dmc_pause_ctrl;
	unsigned int	dddrphy_lock_ctrl;
	unsigned int	c2c_state;
	unsigned char	res62[0x2f60];
	unsigned int	apll_lock;
	unsigned char	res63[0x8];
	unsigned char	res64[0xf4];
	unsigned int	apll_con0;
	unsigned int	apll_con1;
	unsigned char	res65[0xf8];
	unsigned int	src_cpu;
	unsigned char	res66[0x1fc];
	unsigned int	mux_stat_cpu;
	unsigned char	res67[0xfc];
	unsigned int	div_cpu0;
	unsigned int	div_cpu1;
	unsigned char	res68[0xf8];
	unsigned int	div_stat_cpu0;
	unsigned int	div_stat_cpu1;
	unsigned char	res69[0x2f8];
	unsigned int	clk_gate_ip_cpu;
	unsigned char	res70[0xfc];
	unsigned int	clkout_cmu_cpu;
	unsigned int	clkout_cmu_cpu_div_stat;
	unsigned char	res71[0x5f8];
	unsigned int	armclk_stopctrl;
	unsigned int	atclk_stopctrl;
	unsigned char	res72[0x10];
	unsigned char	res73[0x8];
	unsigned int	pwr_ctrl;
	unsigned int	pwr_ctrl2;
	unsigned char	res74[0xd8];
	unsigned int	apll_con0_l8;
	unsigned int	apll_con0_l7;
	unsigned int	apll_con0_l6;
	unsigned int	apll_con0_l5;
	unsigned int	apll_con0_l4;
	unsigned int	apll_con0_l3;
	unsigned int	apll_con0_l2;
	unsigned int	apll_con0_l1;
	unsigned int	iem_control;
	unsigned char	res75[0xdc];
	unsigned int	apll_con1_l8;
	unsigned int	apll_con1_l7;
	unsigned int	apll_con1_l6;
	unsigned int	apll_con1_l5;
	unsigned int	apll_con1_l4;
	unsigned int	apll_con1_l3;
	unsigned int	apll_con1_l2;
	unsigned int	apll_con1_l1;
	unsigned char	res76[0xe0];
	unsigned int	div_iem_l8;
	unsigned int	div_iem_l7;
	unsigned int	div_iem_l6;
	unsigned int	div_iem_l5;
	unsigned int	div_iem_l4;
	unsigned int	div_iem_l3;
	unsigned int	div_iem_l2;
	unsigned int	div_iem_l1;
	unsigned char	res77[0xe0];
	unsigned int	l2_status;
	unsigned char	res78[0xc];
	unsigned int	cpu_status;
	unsigned char	res79[0xc];
	unsigned int	ptm_status;
	unsigned char	res80[0x2edc];
	unsigned int	div_isp0;
	unsigned int	div_isp1;
	unsigned char	res81[0xf8];
	unsigned int	div_stat_isp0;
	unsigned int	div_stat_isp1;
	unsigned char	res82[0x3f8];
	unsigned int	gate_ip_isp0;
	unsigned int	gate_ip_isp1;
	unsigned char	res83[0x1f8];
	unsigned int	clkout_cmu_isp;
	unsigned int	clkout_cmu_ispd_div_stat;
	unsigned char	res84[0xf8];
	unsigned int	cmu_isp_spar0;
	unsigned int	cmu_isp_spar1;
	unsigned int	cmu_isp_spar2;
	unsigned int	cmu_isp_spar3;
};

最后获取重要寄存器值：

void get_clock_init_config(void)
{
	struct exynos4x12_clock *clk = 	(struct exynos4x12_clock *)EXYNOS4X12_CLOCK_BASE;
	
	printf("-----------------------src-------------------------\r\n");
	printf("src_cpu      : %x\r\n", clk->src_cpu);
	printf("src_leftbus  : %x\r\n", clk->src_leftbus);
	printf("src_rightbus : %x\r\n", clk->src_rightbus);
	printf("src_top0     : %x\r\n", clk->src_top0);
	printf("src_top1     : %x\r\n", clk->src_top1);
	printf("src_peril0   : %x\r\n", clk->src_peril0);
	printf("src_peril1   : %x\r\n", clk->src_peril1);
	printf("-----------------------div-------------------------\r\n");
	printf("div_cpu0     : %x\r\n", clk->div_cpu0);
	printf("div_cpu1     : %x\r\n", clk->div_cpu1);
	printf("div_top      : %x\r\n", clk->div_top);
	printf("div_peril0   : %x\r\n", clk->div_peril0);
	printf("div_peril1   : %x\r\n", clk->div_peril1);
	printf("div_peril2   : %x\r\n", clk->div_peril2);
	printf("div_peril3   : %x\r\n", clk->div_peril3);
	printf("div_peril4   : %x\r\n", clk->div_peril4);
	printf("div_peril5   : %x\r\n", clk->div_peril5);	
	printf("div_dmc0     : %x\r\n", clk->div_dmc0);
	printf("div_dmc1     : %x\r\n", clk->div_dmc1);
	printf("------------------------ctrl------------------------\r\n");
	printf("apll_con0    : %x\r\n", clk->apll_con0);
	printf("apll_con1    : %x\r\n", clk->apll_con1);
	printf("mpll_con0    : %x\r\n", clk->mpll_con0);
	printf("mpll_con1    : %x\r\n", clk->mpll_con1);
	
	return 0;
}

然后可以得到结果：

最后根据官方提供的u-boot看完整的时钟设置：

1. CLK_SRC_CPU = 0
    wait


2.CLK_DIV_DMC0 和 CLK_DIV_DMC1
    #define CORE_TIMERS_RATIO	0x0
    #define COPY2_RATIO		0x0
    #define DMCP_RATIO		0x1
    #define DMCD_RATIO		0x1
    #define DMC_RATIO		0x3
    #define DPHY_RATIO		0x1
    #define ACP_PCLK_RATIO		0x1
    #define ACP_RATIO		0x3
    #define CLK_DIV_DMC0_VAL	((CORE_TIMERS_RATIO << 28) \
							| (COPY2_RATIO << 24) \
							| (DMCP_RATIO << 20)	\
							| (DMCD_RATIO << 16)	\
							| (DMC_RATIO << 12)	\
							| (DPHY_RATIO << 8)	\
							| (ACP_PCLK_RATIO << 4)	\
							| (ACP_RATIO))

    #define CLK_DIV_DMC1_VAL	0x07071713

    @CLK_DIV_DMC0 = CLK_DIV_DMC0_VAL
    @CLK_DIV_DMC1_OFFSET = CLK_DIV_DMC1_VAL



3. CLK_SRC_TOP0 和 CLK_SRC_TOP1
    /* CLK_SRC_TOP0	*/
    #define MUX_ONENAND_SEL 0x0 /* 0 = DOUT133, 1 = DOUT166		*/
    #define MUX_ACLK_133_SEL	0x0	/* 0 = SCLKMPLL, 1 = SCLKAPLL	*/
    #define MUX_ACLK_160_SEL	0x0
    #define MUX_ACLK_100_SEL	0x0
    #define MUX_ACLK_200_SEL	0x0
    #define MUX_VPLL_SEL	0x1
    #define MUX_EPLL_SEL	0x1
    #define CLK_SRC_TOP0_VAL	((MUX_ONENAND_SEL << 28)	\
							| (MUX_ACLK_133_SEL << 24)	\
							| (MUX_ACLK_160_SEL << 20)	\
							| (MUX_ACLK_100_SEL << 16)	\
							| (MUX_ACLK_200_SEL << 12)	\
							| (MUX_VPLL_SEL << 8)	\
							| (MUX_EPLL_SEL << 4))
    #define CLK_SRC_TOP1_VAL	(0x01111000)

    
    @CLK_SRC_TOP0 = CLK_SRC_TOP0_VAL
    @CLK_SRC_TOP1 = CLK_SRC_TOP1_VAL

    wait

4.CLK_DIV_TOP
    /* CLK_DIV_TOP	*/
    /* CLK_DIV_TOP	*/
    #define ACLK_400_MCUISP_RATIO	0x1
    #define ACLK_266_GPS_RATIO	0x2
    #define ONENAND_RATIO	0x1
    #define ACLK_133_RATIO	0x5
    #define ACLK_160_RATIO	0x4
    #define ACLK_100_RATIO	0x7
    #define ACLK_200_RATIO	0x4

    #define CLK_DIV_TOP_VAL	((ACLK_400_MCUISP_RATIO << 24) \
							| (ACLK_266_GPS_RATIO << 20) \
							| (ONENAND_RATIO << 16) \
							| (ACLK_133_RATIO << 12) \
							| (ACLK_160_RATIO << 8)	\
							| (ACLK_100_RATIO << 4)	\
							| (ACLK_200_RATIO))
    @CLK_DIV_TOP = CLK_DIV_TOP_VAL


5. CLK_SRC_LEFTBUS
    /* CLK_SRC_LEFTBUS	*/
    #define CLK_SRC_LEFTBUS_VAL	(0x10)

    @CLK_SRC_LEFTBUS = CLK_SRC_LEFTBUS_VAL

    wait

6. CLK_DIV_LEFTBUS
    /* CLK_DIV_LEFRBUS	*/
    #define GPL_RATIO	0x1
    #define GDL_RATIO	0x3
    #define CLK_DIV_LEFRBUS_VAL	((GPL_RATIO << 4) \
								| (GDL_RATIO))
    
    @CLK_DIV_LEFTBUS = CLK_DIV_LEFRBUS_VAL


7.CLK_SRC_RIGHTBUS
    /* CLK_SRC_RIGHTBUS	*/
    #define CLK_SRC_RIGHTBUS_VAL	(0x10)

    @CLK_SRC_RIGHTBUS = CLK_SRC_RIGHTBUS_VAL

    wait


8.CLK_DIV_RIGHTBUS
    /* CLK_DIV_RIGHTBUS	*/
    #define GPR_RATIO	0x1
    #define GDR_RATIO	0x3
    #define CLK_DIV_RIGHTBUS_VAL	((GPR_RATIO << 4) \
								| (GDR_RATIO))
    @CLK_DIV_RIGHTBUS = CLK_DIV_RIGHTBUS_VAL

9.Set PLL locktime
    
    #define APLL_PDIV	0x3
    #define MPLL_PDIV	0x3
    #define EPLL_PDIV	0x2
    #define VPLL_PDIV	0x2

    /* APLL_LOCK	*/
    #define APLL_LOCK_VAL	(APLL_PDIV * 270)
    /* MPLL_LOCK	*/
    #define MPLL_LOCK_VAL	(MPLL_PDIV * 270)
    /* EPLL_LOCK	*/
    #define EPLL_LOCK_VAL	(EPLL_PDIV * 3000)
    /* VPLL_LOCK	*/
    #define VPLL_LOCK_VAL	(VPLL_PDIV * 3000)    

    @APLL_LOCK = APLL_LOCK_VAL
    @MPLL_LOCK = MPLL_LOCK_VAL

    @EPLL_LOCK = EPLL_LOCK_VAL
    @VPLL_LOCK = VPLL_LOCK_VAL


9. CLK_DIV_CPU0和CLK_DIV_CPU1
    /* CLK_DIV_CPU1	*/
    #define CORES_RATIO	0x5
    #define HPM_RATIO	0x0
    #define COPY_RATIO	0x6
    #define APLL_RATIO	0x2
    #define CORE_RATIO	0x0
    #define CORE2_RATIO	0x0
    #define COREM0_RATIO	0x3
    #define COREM1_RATIO	0x7
    #define PERIPH_RATIO	0x7
    #define ATB_RATIO	0x6
    #define PCLK_DBG_RATIO	0x1


    #define CLK_DIV_CPU0_VAL        ((CORE2_RATIO << 28)    \
                                | (APLL_RATIO << 24)    \
                                | (PCLK_DBG_RATIO << 20)\
                                | (ATB_RATIO << 16)     \
                                | (PERIPH_RATIO <<12)   \
				| (COREM1_RATIO << 8)   \
                                | (COREM0_RATIO << 4)   \
                                | (CORE_RATIO))

    #define CLK_DIV_CPU1_VAL	((CORES_RATIO << 8) \
                                |  (HPM_RATIO << 4) \
                                | (COPY_RATIO))

    @CLK_DIV_CPU0_OFFSET = CLK_DIV_CPU0_VAL
    @CLK_DIV_CPU1_OFFSET = CLK_DIV_CPU1_VAL
    



10.Set APLL
    #define APLL_CON1_VAL	(0x00803800)
    /* Set PLL */
    #define set_pll(mdiv, pdiv, sdiv)	(1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
    #define APLL_MDIV	0xAF
    #define APLL_PDIV	0x3
    #define APLL_SDIV	0x0

    #define APLL_CON0_VAL	set_pll(APLL_MDIV,APLL_PDIV,APLL_SDIV)
    @APLL_CON1_OFFSET = APLL_CON1_VAL
    @APLL_CON0_OFFSET = APLL_CON0_VAL


11.check MPLL and if MPLL is not 400 Mhz skip MPLL resetting for C2C operation
    
    @MPLL_CON0 == 0xA0640301 ？？？

    不等就跳过MPLL设置，相等就设置MPLL

12.设置MPLL
    #define MPLL_CON1_VAL (0x00803800)
    #define MPLL_MDIV	0x64     // CONFIG_CLK_BUS_DMC_100_200
    #define MPLL_PDIV	0x3
    #define MPLL_SDIV	0x0
    #define MPLL_CON0_VAL	set_pll(MPLL_MDIV,MPLL_PDIV,MPLL_SDIV)
    @MPLL_CON1 = MPLL_CON1_VAL
    @MPLL_CON0 = MPLL_CON0_VAL

13 设置EPLL
    #define EPLL_CON2_VAL	0x00000080
    #define EPLL_CON1_VAL	0x66010000
    #define EPLL_MDIV	0x40
    #define EPLL_PDIV	0x2
    #define EPLL_SDIV	0x3
    #define EPLL_CON0_VAL	set_pll(EPLL_MDIV,EPLL_PDIV,EPLL_SDIV)
    @EPLL_CON2_OFFSET =  EPLL_CON2_VAL
    @EPLL_CON1_OFFSET = EPLL_CON1_VAL
    @EPLL_CON0_OFFSET = EPLL_CON0_VAL
    

14.设置VPLL
    #define VPLL_CON1_VAL	0x66010000
    #define VPLL_CON2_VAL	0x00000080

    #define VPLL_MDIV	0x48
    #define VPLL_PDIV	0x2
    #define VPLL_SDIV	0x3
    #define VPLL_CON0_VAL	set_pll(VPLL_MDIV,VPLL_PDIV,VPLL_SDIV)
    @VPLL_CON2_OFFSET = VPLL_CON2_VAL
    @VPLL_CON1_OFFSET = VPLL_CON1_VAL
    @VPLL_CON0_OFFSET = VPLL_CON0_VAL


    wait

15.其他
    //（(1<<24) | 1） MUX_MPLL_USER_SEL_C | MUX_APLL_SEL
    @CLK_SRC_CPU_OFFSET = 0x01000001 
    //((1<<16)|(1<<12))  MUX_PWI_SEL = XusbXTI, MUX_MPLL_SEL=MOUTMPLLFOUT
    @CLK_SRC_DMC_OFFSET = 0x00011000 

    //((1<<8)|(1<<4))  MUX_VPLL_SEL=FOUTVPLL, MUX_EPLL_SEL=FOUTEPLL
    @CLK_SRC_TOP0_OFFSET = 0x00000110
    /*
    * ((1<<24)|(1<<20)|(1<<16)|(1<<12)) 
    * MUX_ACLK_400_MCUISP_SUB_SEL = DIVOUT_ACLK_400_MCUISP 
    * MUX_ACLK_200_SUB_SEL=DIVOUT_ACLK_200
    * MUX_ACLK_266_GPS_SUB_SEL=DIVOUT_ACLK_266_GPS
    * MUX_MPLL_USER_SEL_T=SCLKMPLLL
    */ 
    @CLK_SRC_TOP1_OFFSET = 0x01111000


    wait