FPGA Verilog实现数字钟2 校时校分蜂鸣器功能

/************************************************
 
     Design by Romy
          
   2015.10.05

**************************************************/




module column_scan_module
(
    CLK, RSTn, 
Column_Scan_Sig,Row_Scan_Sig, EN, S1,S2,spk
);
    
input CLK;
input RSTn;
input EN;
input S1;
input S2;
output spk;

output [5:0]Column_Scan_Sig;
output [7:0]Row_Scan_Sig;
 
/*****************************/
 
  parameter T4MS = 18'd19_9999;
 
/*************** Clock **************/
/*************** Clock **************/
 
reg [18:0]Count1;
 
always @ ( posedge CLK or negedge RSTn )
    if( !RSTn )
     Count1 <= 18'd0;
 else if( Count1 == T4MS )
     Count1 <= 18'd0;
 else
     Count1 <= Count1 + 1'b1;

/************** SMG choose ****************/
/************** SMG choose ****************/
 
reg [2:0]t;
 
always @ ( posedge CLK or negedge RSTn )
    if( !RSTn )
     t <= 3'd0;
 else if( t == 3'd6 )
     t <= 3'd0;
 else if( Count1 == T4MS )
     t <= t + 1'b1;

/************** SMG choose ****************/
 
reg [5:0]rColumn_Scan;
 
always @ ( posedge CLK or negedge RSTn )
    if( !RSTn )
     rColumn_Scan <= 6'b111111;
 else if( Count1 == T4MS )
     case( t )

   3'd0 : rColumn_Scan <= 6'b111110;
3'd1 : rColumn_Scan <= 6'b111101;
   3'd2 : rColumn_Scan <= 6'b111011;
3'd3 : rColumn_Scan <= 6'b110111;
3'd4 : rColumn_Scan <= 6'b101111;
3'd5 : rColumn_Scan <= 6'b011111;
endcase  

 /***************************************/
 
 assign Column_Scan_Sig =  rColumn_Scan;
 
 /****************** Counter *********************/
 /***************** Counter **********************/
  
parameter T1S = 28'd49_999_999;

 /*****************Second**********************/
 
reg [27:0]Count2;
 
always @ ( posedge CLK or negedge RSTn )
    if( !RSTn )
     Count2 <= 28'd0;
 else if( Count2 == T1S )
     Count2 <= 28'd0;
 else
     Count2 <= Count2 + 1'b1; 

  /***************** Counter **********************/