在vivado编译时Generate Bitstream中运行不出来

最新推荐文章于 2024-07-18 19:36:12 发布

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最新推荐文章于 2024-07-18 19:36:12 发布

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分类专栏： FPGA 文章标签： vivado zynq

本文链接：https://blog.csdn.net/sinat_38694059/article/details/94622384

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在Vivado编译过程中遇到Generate Bitstream无法运行的警告，警告指出设计中有未约束的逻辑端口可能导致I/O冲突或设备损坏。通过在xdc文档中插入命令`set_property SEVERITY {Warning} [get_drc_checks UCIO-1]`，可以将警告级别设置为警告并允许比特流生成，但建议指定所有引脚位置以避免潜在问题。问题端口涉及sys_clk。

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在vivado编译时Generate Bitstream中运行不出来
警告：
[DRC UCIO-1] Unconstrained Logical Port: 1 out of 5 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: sys_clk.
使用谷歌翻译之后是：
[DRC UCIO-1]无约束逻辑端