功能:每隔一秒发送 hello world,如果串口接收到数据,在没有发送hello world的时候将接收的数据发送出去。
9600bps,无校验位
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 19:53:54 08/14/2019
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module top(
input clk,
input rst_n,
input rx,
output tx
);
reg [7:0] str [12:0];
initial begin
str[0] <= 8'h48; //h
str[1] <= 8'h45; //e
str[2] <= 8'h4c; //l
str[3] <= 8'h4c; //l
str[4] <= 8'h4f; //o
str[5] <= 8'h20; //space
str[6] <= 8'h57; //w
str[7] <= 8'h4f; //o
str[8] <= 8'h52; //r
str[9] <= 8'h4c; //l
str[10] <= 8'h44; //d
str[11] <= 8'h0d; //enter
str[12] <= 8'h0a; //enter
end
wire clk_div;
clk_div clk_div_inst(
.clk(clk),
.rst_n(rst_n),
.clk_div(clk_div)
);
wire uart_tx_full;
reg [7:0] tx_data;
reg tx_data_en;
uart_tx uart_tx_inst(
.clk(clk_div),
.rst_n(rst_n),
.tx_data(tx_data),
.data_en(tx_data_en),
.full(uart_tx_full),
.tx(tx)
);
wire [7:0] rx_fifo_dout;
wire empty;
wire rd_en;
uart_rx uart_rx_inst(
.clk(clk_div),
.rst_n(rst_n),
.rx_fifo_dout(rx_fifo_dout),
.rx(rx),
.empty(empty),
.rd_en(rd_en)
);
reg [17:0] cnt;
reg [3:0] state;
reg tx_busy;
always @(posedge clk_div or negedge rst_n)
begin
if(!rst_n) begin
state <= 4'd0;
cnt <= 18'd0;
tx_busy <= 1'd0;
tx_data_en <= 1'd0;
tx_data <= 8'd0;
end
else begin
case(state)
4'd0: begin
if(~empty) begin
state <= 4'd2;
end
else if(cnt == 18'd153599) begin
cnt <= 18'd0;
state <= 4'd1;
tx_busy <= 1'd1;
end
else begin
cnt <= cnt + 18'd1;
end
tx_data_en <= 1'd0;
tx_data <= 8'd0;
end
4'd1: begin
if(cnt == 18'd13) begin
tx_data_en <= 1'd0;
cnt <= 18'd0;
state <= 4'd0;
tx_busy <= 1'd0;
end
else begin
if(~uart_tx_full) begin
cnt <= cnt + 18'd1;
tx_data <= str[cnt];
tx_data_en <= 1'd1;
end
else begin
tx_data_en <= 1'd0;
end
end
end
4'd2: begin
if(empty) state <= 4'd0;
cnt <= 18'd0;
tx_data_en <= rd_en;
tx_data <= rx_fifo_dout;
end
endcase
end
end
assign rd_en = (state == 4'd2) & (~empty);
endmodule
clk_div:波特率9600bps,50mhz主频分频后每16个周期发送或者接收一位
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 15:24:21 08/19/2019
// Design Name:
// Module Name: clk_div
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module clk_div(
input clk,
input rst_n,
output clk_div
);
reg [7:0] cnt;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n) cnt <= 8'd0;
else begin
if(cnt == 8'd162) cnt <= 8'd0;
else cnt <= cnt + 8'd1;
end
end
reg clk_div_r;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n) clk_div_r <= 1'd0;
else if(cnt == 8'd162) clk_div_r <= ~clk_div_r;
end
assign clk_div = clk_div_r;
endmodule
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 14:39:35 08/19/2019
// Design Name:
// Module Name: uart_tx
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module uart_tx(
input clk,
input rst_n,
input [7:0] tx_data,
input data_en,
output full,
output tx
);
wire busy;
wire [7 : 0] tx_fifo_dout;
//wire tx_fifo_full;
wire tx_fifo_empty;
wire tx_fifo_rd_en;
assign tx_fifo_rd_en = ~tx_fifo_empty & ~busy;
tx_fifo tx_fifo_inst(
.rst(~rst_n),
.wr_clk(clk),
.rd_clk(clk),
.din(tx_data),
.wr_en(data_en),
.rd_en(tx_fifo_rd_en),
.dout(tx_fifo_dout),
.full(full),
.empty(tx_fifo_empty)
);
tx_data tx_data_inst(
.clk(clk),
.rst_n(rst_n),
.busy(busy),
.data(tx_fifo_dout),
.data_en(tx_fifo_rd_en),
.tx(tx)
);
endmodule
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 15:34:59 08/19/2019
// Design Name:
// Module Name: tx_data
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module tx_data(
input clk,
input rst_n,
output busy,
input [7:0] data,
input data_en,
output reg tx
);
reg [3:0] cnt;
reg [3:0] state;
reg [7:0] data_r;
reg busy_r;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n) begin
state <= 4'd0;
cnt <= 4'd0;
tx <= 1'd1;
data_r <= 8'd0;
busy_r <= 1'd0;
end
else begin
case(state)
4'd0: begin
if(data_en) begin
state <= state + 1'd1;
tx <= 1'd0;
//data_r <= data;
busy_r <= 1'd1;
end
else begin
//cnt <= cnt + 4'd1;
tx <= 1'd1;
end
end
4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7, 4'd8: begin
if(cnt == 4'd15) begin
cnt <= 4'd0;
state <= state + 1'd1;
tx <= data_r[state - 1'd1];
end
else begin
cnt <= cnt + 4'd1;
data_r <= data;
end
end
4'd9: begin //stop
if(cnt == 4'd15) begin
cnt <= 4'd0;
state <= state + 1'd1;
tx <= 1'd1;
end
else begin
cnt <= cnt + 4'd1;
end
end
4'd10: begin //stop
if(cnt == 4'd15) begin
cnt <= 4'd0;
state <= 4'd0;
busy_r <= 1'd0;
end
else begin
cnt <= cnt + 4'd1;
end
end
endcase
end
end
assign busy = busy_r;
endmodule
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 17:02:30 08/19/2019
// Design Name:
// Module Name: uart_rx
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module uart_rx(
input clk,
input rst_n,
output [7:0] rx_fifo_dout,
//output data_en,
input rx,
output empty,
input rd_en
);
wire [7:0] rx_data;
wire data_en;
//wire rd_en;
wire full;
tx_fifo rx_fifo_inst(
.rst(~rst_n),
.wr_clk(clk),
.rd_clk(clk),
.din(rx_data),
.wr_en(data_en),
.rd_en(rd_en),
.dout(rx_fifo_dout),
.full(full),
.empty(empty)
);
//wire capture;
rx_data rx_data_inst(
.clk(clk),
.rst_n(rst_n),
.rx_data(rx_data),
.data_en(data_en),
.rx(rx)
);
endmodule
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 17:37:32 08/19/2019
// Design Name:
// Module Name: rx_data
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module rx_data(
input clk,
input rst_n,
output [7:0] rx_data,
output data_en,
input rx
);
reg data_en_r;
reg [3:0] state;
reg [4:0] cnt;
reg [7:0] rx_data_r;
//reg capture;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n) begin
state <= 4'd0;
cnt <= 5'd0;
rx_data_r <= 8'd0;
data_en_r <= 1'd0;
end
else begin
case(state)
4'd0: begin
if(!rx) begin
state <= state + 4'd1;
cnt <= 5'd0;
rx_data_r <= 8'd0;
end
data_en_r <= 1'd0;
end
4'd1: begin
if(cnt == 5'd23) begin
state <= state + 4'd1;
rx_data_r[0] <= rx;
cnt <= 5'd0;
end
else begin
cnt <= cnt + 5'd1;
end
end
4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8: begin
if(cnt == 5'd15) begin
state <= state + 4'd1;
rx_data_r[state - 1'd1] <= rx;
cnt <= 5'd0;
end
else begin
cnt <= cnt + 5'd1;
end
end
4'd9: begin
if(cnt == 5'd15) begin
state <= 4'd0;
data_en_r <= 1'd1;
cnt <= 5'd0;
end
else begin
cnt <= cnt + 5'd1;
end
end
endcase
end
end
assign data_en = data_en_r;
assign rx_data = rx_data_r;
endmodule
NET "clk" LOC = V10 | TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 50000 kHz;
##
NET rst_n LOC = N4 | IOSTANDARD = "LVCMOS15"; ## SW2 pushbutton
##
########USB Uart SerialPin define#####################
NET rx LOC = B2 | IOSTANDARD = "LVCMOS33"; ## Uart RXD:U8_TXD
NET tx LOC = C4 | IOSTANDARD = "LVCMOS33"; ## Uart TXD:U8_RXD
#NET UART_CTS LOC = D6 | IOSTANDARD = "LVCMOS33"; ## Uart CTS:U8_CTS
#NET UART_RTS LOC = A2 | IOSTANDARD = "LVCMOS33"; ## Uart RTS:U8_RTS