Armv7 Exception Return Address

Exception	Return Instruction	Instruction returned to	Why(Find in TRM)
SVC	MOVS PC, R14	Next Instruction	TakeSVCException:R14 = PC - 4	the program counter is not updated when the exception is taken, so lr point the next instruction
Undef	MOVS PC, R14	Next Instruction	TakeUndefInstrException:R14 = PC - 4	same as SVC
Prefetch Abort	SUBS PC, R14, #4	Aborting instruction	TakePrefetchAbortException: R14 = PC - 4	save as SVC,the difference is returning to the aborting instruction, not the next instruction
Data abort	SUBS PC, R14, #8	Aborting instruction if precise	TakeDataAbortException : R14 = PC	save as Prefetch Abort , but lr = PC not PC - 4
FIQ	SUBS PC, R14, #4	Next Instruction	TakeIRQException : R14 = PC - 4	IRQ or FIQ exceptions are generated only after the program counter has been updated, so lr point two instructions beyond where the exception occurred, execution must continue from the instruction prior to the one pointed to by lr
IRQ	SUBS PC, R14, #4	Next Instruction	TakeFIQException : R14 = PC - 4	same as FIQ