![](https://img-blog.csdnimg.cn/20201014180756923.png?x-oss-process=image/resize,m_fixed,h_64,w_64)
Verilog HDLbits
文章平均质量分 67
个人在HDLbits上的心酸代码史
sss-fish
这个作者很懒,什么都没留下…
展开
-
Fsm serialdp
题目:See also:Serial receiver and datapath,We want to add parity checking to the serial receiver. Parity checking adds one extra bit after each data byte. We will use odd parity, where the number of1s in the 9 bits received must be odd. For example,10100...原创 2021-11-21 13:21:43 · 626 阅读 · 0 评论 -
Fsm serial
题目: In many (older) serial communications protocols, each data byte is sent along with a start bit and a stop bit, to help the receiver delimit bytes from the stream of bits. One common scheme is to use one start bit (0), 8 data bits, and 1 stop ...原创 2021-11-17 20:35:41 · 468 阅读 · 1 评论 -
Lemmings4
题目See also:Lemmings1,Lemmings2, andLemmings3.Although Lemmings can walk, fall, and dig, Lemmings aren't invulnerable. If a Lemming falls for too long then hits the ground, it can splatter. In particular, if a Lemming falls for more than 20 clock cycle...原创 2021-11-15 11:02:13 · 527 阅读 · 0 评论 -
Lemmings2
题目See also:Lemmings1.In addition to walking left and right, Lemmings will fall (and presumably go "aaah!") if the ground disappears underneath them.In addition to walking left and right and changing direction when bumped, whenground=0, the Lemming will..原创 2021-11-13 19:43:43 · 549 阅读 · 0 评论 -
Exams/ece241 2013 q4
题目翻译: 一个大水库供几个人用。为了保持足够的储水量,三个传感器以5英寸的间隔垂直安装。当水位高于最高的传感器(S3)时,输入水量应为零。当液位低于最低传感器(S1)时,流量应该达到最大(公称流量阀fr和补充流量阀dfr都打开)。当水位处于上下传感器之间时,流量由两个因素决定:水位和上一次传感器变化前的水位。每个水位都有一个与之相关的额定输入水量,如下表所示。如果传感器的变化表明先前的液位低于当前的液位,输入水量应该被改为当前水位对应输水量。如果之前的液位高于当前的液位,应通过打开...原创 2021-11-12 11:52:24 · 671 阅读 · 0 评论 -
Count clock(Verilog HDLs)
创建一组适合用作 12 小时制的计数器(带有 am/pm 指示器)。 您的计数器由快速运行的 clk 计时,每当您的时钟应增加(即每秒一次)时,就会在 ena 上发出脉冲。reset 将时钟重置为 12:00 AM。 pm 是 0 代表上午,1 代表下午。 hh、mm 和 ss 是两个 BC(二进制编码的十进制)数字,每个数字表示小时 (01-12)、分钟 (00-59) 和秒 (00-59)。 复位的优先级高于使能,即使未使能也可能发生。以下时序图显示了从上午 11:59:59 到下午 1...原创 2021-11-04 13:01:11 · 712 阅读 · 0 评论 -
Exams/ece241 2014 q1c (HDLbits)
Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0]. These numbers are added to produce s[7:0]. Also compute whether a (signed) overflow has occurred.假设您有两个 8 位 2 的补码,a[7:0] 和 b[7:0]。 这些数字相加产生 s[7:0]。 还要计算是否发生了(有符号的)溢出。题目解析:根据补码的原创 2021-10-16 21:00:13 · 795 阅读 · 1 评论