Fsm serial

题目：

         In many (older) serial communications protocols, each data byte is sent along with a start bit and a stop bit, to help the receiver delimit bytes from the stream of bits. One common scheme is to use one start bit (0), 8 data bits, and 1 stop bit (1). The line is also at logic 1 when nothing is being transmitted (idle).Design a finite state machine that will identify when bytes have been correctly received when given a stream of bits. It needs to identify the start bit, wait for all 8 data bits, then verify that the stop bit was correct. If the stop bit does not appear when expected, the FSM must wait until it finds a stop bit before attempting to receive the next byte.

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题目翻译： 

       在许多（较旧的）串行通信协议中，每个数据字节都与一个起始位和一个停止位一起发送，以帮助接收器从位流中分隔字节。 一种常见的方案是使用 1 个起始位 (0)、8 个数据位和 1 个停止位 (1)。 当没有传输任何内容（空闲）时，该线路也处于逻辑 1。设计一个有限状态机，当给定比特流时，它将识别何时正确接收字节。 它需要识别起始位，等待所有 8 个数据位，然后验证停止位是否正确。 如果停止位没有按预期出现，FSM 必须等待直到找到停止位，然后才能尝试接收下一个字节。

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逻辑抽象：

               一个完整数据包括起始位、8个数据位和一个停止位共10个位

               未进入起始位时，系统处于空闲状态

               进入停止位后，进行判别，如果停止位正确，按照in的输入选择进入S0或S1

               如果停止位不正确，进入等待状态，直到找到in，并结束该次数据输入，返回S0或S1

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有限状态机：

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注意事项：

               一个成功的数据传输包括起始位，8个数据位，停止位10个状态，起始位和停止位也占一个周期，不能空闲状态判定in后直接进入数据位进行数据传输，同理第8个数据位完成后需要进入停止位，而不能直接判断进入错误位或返回

 

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module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output reg done
); 
reg [3:0] state,next_state;
parameter S11=11,S0=0,S1=1,S2=2,S3=3,S4=4,S5=5,S6=6,S7=7,S8=8,S9=9,S10=10;
always @(*)
begin
case(state)
S0:next_state<=(!in)?S1:S0;
S1:next_state<=S2;
S2:next_state<=S3;
S3:next_state<=S4;
S4:next_state<=S5;
S5:next_state<=S6;
S6:next_state<=S7;
S7:next_state<=S8;
S8:next_state<=S9;
S9:next_state<=(in)?S10:S11;
S10:next_state<=(!in)?S1:S0;
S11:next_state<=(in)?S0:S11;
default;
endcase
end

always@(posedge clk)
begin
if(reset)
state<=S0;
else state<=next_state;
end

always@(posedge clk)
begin
if(reset)
done<=0;
else if(next_state==S10)
done<=1;
else done<=0;
end

endmodule

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本人vegetable，勿喷