1、内存资源
4M片上flash,接到flexspi2,地址范围是 0x7000 0000 - 0x703F FFFF
1M片上RAM。
2、MIMXRT1064xxxxx_flexspi_nor.icf文件
/*
** ###################################################################
** Processors: MIMXRT1064CVJ5A
** MIMXRT1064CVL5A
** MIMXRT1064DVJ6A
** MIMXRT1064DVL6A
**
** Compiler: IAR ANSI C/C++ Compiler for ARM
** Reference manual: IMXRT1064RM Rev.0.1, 12/2018 | IMXRT1064SRM Rev.3
** Version: rev. 0.1, 2018-06-22
** Build: b210227
**
** Abstract:
** Linker file for the IAR ANSI C/C++ Compiler for ARM
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2021 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** ###################################################################
*/
/*定义向量表大小和偏移*/
define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0;
define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0;
/*定义中断起始和结束地址*/
define symbol m_interrupts_start = 0x70002000;
define symbol m_interrupts_end = 0x700023FF;
/*定义代码起始地址和结束地址,注意代码在中断之后*/
define symbol m_text_start = 0x70002400;
define symbol m_text_end = 0x703FFFFF;
/*定义RAM中断起始和结束地址*/
define symbol m_interrupts_ram_start = 0x20000000;
define symbol m_interrupts_ram_end = 0x20000000 + __ram_vector_table_offset__;
/*定义DATA起始和结束地址,实际是DTCM,默认分配128KB,我们定义的变量,堆栈使用的都是这部分内存,可以适当加大,比如256KB
RT1064OCRAM固定有521KB,另外512KB可以灵活分配给DTCM,OCRAM,ITCM,ITCM默认分配128KB,一般不去改变,剩下384KB可以全部分给DTCM,这样定义大数组时就不报内存不足了
*/
define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__;
define symbol m_data_end = 0x2001FFFF;
/*定义DATA2起始和结束地址,实际是OCRAM,默认分配512+256KB*/
define symbol m_data2_start = 0x20200000;
define symbol m_data2_end = 0x202BFFFF;
/*定义quic access code起始和结束地址,实际是ITCM,默认分配128KB*/
define symbol m_qacode_start = 0x00000000;
define symbol m_qacode_end = 0x0001FFFF;
define exported symbol m_boot_hdr_conf_start = 0x70000000;
define symbol m_boot_hdr_ivt_start = 0x70001000;
define symbol m_boot_hdr_boot_data_start = 0x70001020;
define symbol m_boot_hdr_dcd_data_start = 0x70001030;
/* Sizes 定义堆栈大小,1K不够大,可以设置为20K*/
if (isdefinedsymbol(__stack_size__)) {
define symbol __size_cstack__ = __stack_size__;
} else {
define symbol __size_cstack__ = 0x0400;
}
if (isdefinedsymbol(__heap_size__)) {
define symbol __size_heap__ = __heap_size__;
} else {
define symbol __size_heap__ = 0x0400;
}
define exported symbol __NCACHE_REGION_START = m_data2_start;
define exported symbol __NCACHE_REGION_SIZE = 0x0;
define exported symbol __VECTOR_TABLE = m_interrupts_start;
define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
define memory mem with size = 4G;
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
| mem:[from m_text_start to m_text_end];
define region QACODE_region = mem:[from m_qacode_start to m_qacode_end];
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
define region DATA2_region = mem:[from m_data2_start to m_data2_end];
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end]; /*从这里看出栈是DTCM末尾的一块内存*/
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block RW { readwrite };
define block ZI { zi };
define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
define block QACCESS_CODE { section CodeQuickAccess };
initialize by copy { readwrite, section .textrw, section CodeQuickAccess };
do not initialize { section .noinit };
place at address mem: m_interrupts_start { readonly section .intvec };
place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };
keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };
place in TEXT_region { readonly };
place in DATA_region { block RW };
place in DATA_region { block ZI };
place in DATA_region { last block HEAP };
place in DATA_region { block NCACHE_VAR };
place in CSTACK_region { block CSTACK };
place in QACODE_region { section .textrw};
place in QACODE_region { block QACCESS_CODE };