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FPGA实验五 多周期移位寄存器
实验要求:
设计时间基准电路和带使能的多周期移位寄存器
•电路工作在50MHz
•在每个时间基准信号有效的时钟周期
–把一个拨码开关的状态值移位输入到寄存器的最低位
–顺序移动移位寄存器的值
–寄存器的每个比特送至一个LED灯上显示
设计新的功能
–在原有的电路基础上,添加方向选择功能。
–SW0仍然是移位寄存器组的输入
–使用SW1开关,控制移位寄存的方向
–从实验现象上应当能够看到,SW1可以控制LED闪烁的移动方向,以及控制SW0值的对LED组的输入位置(即从LED组的最左边或是最右边)
串入并出移位寄存器 /
module shift_reg_SIPO(
RST , // 异步复位, 高有效
CLK , // 时钟,上升沿有效
EN , // 输入数据串行移位使能
IN , // 输入串行数据
EN_L ,
OUT ); // 并行输出数据
parameter SHLEN = 6;
input RST, CLK, EN;
input IN, EN_L;
output[SHLEN-1:0] OUT;
reg [SHLEN-1:0] shift_R;
assign OUT[SHLEN-1:0] = shift_R[SHLEN-1:0];
// 时序逻辑 根据输入使能进行串行移位
// shift_R 会被编译为D触发器
always @ (posedge CLK or posedge RST)
begin
if(RST)
begin
shift_R[SHLEN-1:0] <= 0;
end
else
begin
if(EN)
begin // 串行移位的使能有效
if(EN_L)//左输入
begin
shift_R[SHLEN-2 : 0] <= shift_R[SHLEN-1 : 1];
shift_R[SHLEN-1] <= IN;
end
else//右输入
begin
shift_R[SHLEN-1 : 1] <= shift_R[SHLEN-2 : 0];
shift_R[0] <= IN;
end
end
else
begin // 使能无效保持不动
shift_R[SHLEN-1:0] <= shift_R[SHLEN-1:0];
end
end
end // always
endmodule
左移
右移
FPGA实验六 计数器、ROM和DDS
本实验设计目标
认识ROM
•用计数器生成地址、读叏ROM数据
•用SignalTAP观察ROM的输出波形
•理解二进制补码和无符号数
•修改计数增量值,观察波形变化,思考输出频率和计数器增量值的关系。
// ************************************************************** //
// FILE : sine_rom.v
// DSCP : sine_rom FILE
// ABOUT : auto generated rom file by gen_rom_rtl.m
// DATE : 14-Nov-2013 16:29:45
// ************************************************************** //
// module sine_rom()
module sine_rom(
CLK , // clock
RA , // read address
RD ); // read data
input CLK;
input [6 :0] RA;
output [7 :0] RD;
reg [7 :0] RD;
always @ (posedge CLK)
case(RA)
7 'd 0 :RD = #1 8 'b 00000000; // 0 0x0
7 'd 1 :RD = #1 8 'b 00000110; // 6 0x6
7 'd 2 :RD = #1 8 'b 00001100; // 12 0xC
7 'd 3 :RD = #1 8 'b 00010010; // 18 0x12
7 'd 4 :RD = #1 8 'b 00011000; // 24 0x18
7 'd 5 :RD = #1 8 'b 00011110; // 30 0x1E
7 'd 6 :RD = #1 8 'b 00100100; // 36 0x24
7 'd 7 :RD = #1 8 'b 00101010; // 42 0x2A
7 'd 8 :RD = #1 8 'b 00110000; // 48 0x30
7 'd 9 :RD = #1 8 'b 00110110; // 54 0x36
7 'd 10 :RD = #1 8 'b 00111011; // 59 0x3B
7 'd 11 :RD = #1 8 'b 01000001; // 65 0x41
7 'd 12 :RD = #1 8 'b 01000110; // 70 0x46
7 'd 13 :RD = #1 8 'b 01001011; // 75 0x4B
7 'd 14 :RD = #1 8 'b 01010000; // 80 0x50
7 'd 15 :RD = #1 8 'b 01010101; // 85 0x55
7 'd 16 :RD = #1 8 'b 01011001; // 89 0x59
7 'd 17 :RD = #1 8 'b 01011110; // 94 0x5E
7 'd 18 :RD = #1 8 'b 01100010; // 98 0x62
7 'd 19 :RD = #1 8 'b 01100110; // 102 0x66
7 'd 20 :RD = #1 8 'b 01101001; // 105 0x69
7 'd 21 :RD = #1 8 'b 01101100; // 108 0x6C
7 'd 22 :RD = #1 8 'b 01110000; // 112 0x70
7 'd 23 :RD = #1 8 'b 01110010; // 114 0x72
7 'd 24 :RD = #1 8 'b 01110101; // 117 0x75
7 'd 25 :RD = #1 8 'b 01110111; // 119 0x77
7 'd 26 :RD = #1 8 'b 01111001; // 121 0x79
7 'd 27 :RD = #1 8 'b 01111011; // 123 0x7B
7 'd 28 :RD = #1 8 'b 01111100; // 124 0x7C
7 'd 29 :RD = #1 8 'b 01111101; // 125 0x7D
7 'd 30 :RD = #1 8 'b 01111110; // 126 0x7E
7 'd 31 :RD = #1 8 'b 01111110; // 126 0x7E
7 'd 32 :RD = #1 8 'b 01111111; // 127 0x7F
7 'd 33 :RD = #1 8 'b 01111110; // 126 0x7E
7 'd 34 :RD = #1 8 'b 01111110; // 126 0x7E
7 'd 35 :RD = #1 8 'b 01111101; // 125 0x7D
7 'd 36 :RD = #1 8 'b 01111100; // 124 0x7C
7 'd 37 :RD = #1 8 'b 01111011; // 123 0x7B
7 'd 38 :RD = #1 8 'b 01111001; // 121 0x79
7 'd 39 :RD = #1 8 'b 01110111; // 119 0x77
7 'd 40 :RD = #1 8 'b 01110101; // 117 0x75
7 'd 41 :RD = #1 8 'b 01110010; // 114 0x72
7 'd 42 :RD = #1 8 'b 01110000; // 112 0x70
7 'd 43 :RD = #1 8 'b 01101100; // 108 0x6C
7 'd 44 :RD = #1 8 'b 01101001; // 105 0x69
7 'd 45 :RD = #1 8 'b 01100110; // 102 0x66
7 'd 46 :RD = #1 8 'b 01100010; // 98 0x62
7 'd 47 :RD = #1 8 'b 01011110; // 94 0x5E
7 'd 48 :RD = #1 8 'b 01011001; // 89 0x59
7 'd 49 :RD = #1 8 'b 01010101; // 85 0x55
7 'd 50 :RD = #1 8 'b 01010000; // 80 0x50
7 'd 51 :RD = #1 8 'b 01001011; // 75 0x4B
7 'd 52 :RD = #1 8 'b 01000110; // 70 0x46
7 'd 53 :RD = #1 8 'b 01000001; // 65 0x41
7 'd 54 :RD = #1 8 'b 00111011; // 59 0x3B
7 'd 55 :RD = #1 8 'b 00110110; // 54 0x36
7 'd 56 :RD = #1 8 'b 00110000; // 48 0x30
7 'd 57 :RD = #1 8 'b 00101010; // 42 0x2A
7 'd 58 :RD = #1 8 'b 00100100; // 36 0x24
7 'd 59 :RD = #1 8 'b 00011110; // 30 0x1E
7 'd 60 :RD = #1 8 'b 00011000; // 24 0x18
7 'd 61 :RD = #1 8 'b 00010010; // 18 0x12
7 'd 62 :RD = #1 8 'b 00001100; // 12 0xC
7 'd 63 :RD = #1 8 'b 00000110; // 6 0x6
7 'd 64 :RD = #1 8 'b 00000000; // 0 0x0
7 'd 65 :RD = #1 8 'b 11111010; // -6 0xFA
7 'd 66 :RD = #1 8 'b 11110100; // -12 0xF4
7 'd 67 :RD = #1 8 'b 11101110; // -18 0xEE
7 'd 68 :RD = #1 8 'b 11101000; // -24 0xE8
7 'd 69 :RD = #1 8 'b 11100010; // -30 0xE2
7 'd 70 :RD = #1 8 'b 11011100; // -36 0xDC
7 'd 71 :RD = #1 8 'b 11010110; // -42 0xD6
7 'd 72 :RD = #1 8 'b 11010000; // -48 0xD0
7 'd 73 :RD = #1 8 'b 11001010; // -54 0xCA
7 'd 74 :RD = #1 8 'b 11000101; // -59 0xC5
7 'd 75 :RD = #1 8 'b 10111111; // -65 0xBF
7 'd 76 :RD = #1 8 'b 10111010; // -70 0xBA
7 'd 77 :RD = #1 8 'b 10110101; // -75 0xB5
7 'd 78 :RD = #1 8 'b 10110000; // -80 0xB0
7 'd 79 :RD = #1 8 'b 10101011; // -85 0xAB
7 'd 80 :RD = #1 8 'b 10100111; // -89 0xA7
7 'd 81 :RD = #1 8 'b 10100010; // -94 0xA2
7 'd 82 :RD = #1 8 'b 10011110; // -98 0x9E
7 'd 83 :RD = #1 8 'b 10011010; // -102 0x9A
7 'd 84 :RD = #1 8 'b 10010111; // -105 0x97
7 'd 85 :RD = #1 8 'b 10010100; // -108 0x94
7 'd 86 :RD = #1 8 'b 10010000; // -112 0x90
7 'd 87 :RD = #1 8 'b 10001110; // -114 0x8E
7 'd 88 :RD = #1 8 'b 10001011; // -117 0x8B
7 'd 89 :RD = #1 8 'b 10001001; // -119 0x89
7 'd 90 :RD = #1 8 'b 10000111; // -121 0x87
7 'd 91 :RD = #1 8 'b 10000101; // -123 0x85
7 'd 92 :RD = #1 8 'b 10000100; // -124 0x84
7 'd 93 :RD = #1 8 'b 10000011; // -125 0x83
7 'd 94 :RD = #1 8 'b 10000010; // -126 0x82
7 'd 95 :RD = #1 8 'b 10000010; // -126 0x82
7 'd 96 :RD = #1 8 'b 10000001; // -127 0x81
7 'd 97 :RD = #1 8 'b 10000010; // -126 0x82
7 'd 98 :RD = #1 8 'b 10000010; // -126 0x82
7 'd 99 :RD = #1 8 'b 10000011; // -125 0x83
7 'd 100 :RD = #1 8 'b 10000100; // -124 0x84
7 'd 101 :RD = #1 8 'b 10000101; // -123 0x85
7 'd 102 :RD = #1 8 'b 10000111; // -121 0x87
7 'd 103 :RD = #1 8 'b 10001001; // -119 0x89
7 'd 104 :RD = #1 8 'b 10001011; // -117 0x8B
7 'd 105 :RD = #1 8 'b 10001110; // -114 0x8E
7 'd 106 :RD = #1 8 'b 10010000; // -112 0x90
7 'd 107 :RD = #1 8 'b 10010100; // -108 0x94
7 'd 108 :RD = #1 8 'b 10010111; // -105 0x97
7 'd 109 :RD = #1 8 'b 10011010; // -102 0x9A
7 'd 110 :RD = #1 8 'b 10011110; // -98 0x9E
7 'd 111 :RD = #1 8 'b 10100010; // -94 0xA2
7 'd 112 :RD = #1 8 'b 10100111; // -89 0xA7
7 'd 113 :RD = #1 8 'b 10101011; // -85 0xAB
7 'd 114 :RD = #1 8 'b 10110000; // -80 0xB0
7 'd 115 :RD = #1 8 'b 10110101; // -75 0xB5
7 'd 116 :RD = #1 8 'b 10111010; // -70 0xBA
7 'd 117 :RD = #1 8 'b 10111111; // -65 0xBF
7 'd 118 :RD = #1 8 'b 11000101; // -59 0xC5
7 'd 119 :RD = #1 8 'b 11001010; // -54 0xCA
7 'd 120 :RD = #1 8 'b 11010000; // -48 0xD0
7 'd 121 :RD = #1 8 'b 11010110; // -42 0xD6
7 'd 122 :RD = #1 8 'b 11011100; // -36 0xDC
7 'd 123 :RD = #1 8 'b 11100010; // -30 0xE2
7 'd 124 :RD = #1 8 'b 11101000; // -24 0xE8
7 'd 125 :RD = #1 8 'b 11101110; // -18 0xEE
7 'd 126 :RD = #1 8 'b 11110100; // -12 0xF4
7 'd 127 :RD = #1 8 'b 11111010; // -6 0xFA
default : RD = #1 0;
endcase
endmodule
带计数增量输入的计数器 /
module cnt_incr(
CLK , // clock
INCR , // counter increase value
CNTVAL); // counter value
input CLK;
input [7-1:0] INCR;
output [7-1:0] CNTVAL;
reg [7-1:0] CNTVAL;
always @ (posedge CLK) begin
CNTVAL <= INCR + CNTVAL;
end
endmodule // module cnt_incr
注意添加探测节点,ROMOUT和RAOUT,这两个输出信号丌用指派管脚,仅用作调试观测节点。
当计数到最大值时,计数器会向0回绕,重新累加计数,例如:若计数位宽为3比特、增量为2,则最大计数值为7,计数过程为,0,2,4,6,1,3,5,7,2,4,6,1,3,5,7,……
计数增量信号从比特6—比特0,指派到拨码开关的第6位—第0位
新建一个文本文件,例如pin_de0.txt,内容的第一行是to, location 然后下面内容就是输出信号名称和管脚位置对应关系
通过Import assignments来把该文本文件导入
to,location
# 50MHz clock_input
CLOCK_50 , PIN_G21
CLOCK_50_2 , PIN_B21
#slide switch[0] to slide switch[9]
SW[0] , PIN_J6
SW[1] , PIN_H5
SW[2] , PIN_H6
SW[3] , PIN_G4
SW[4] , PIN_G5
SW[5] , PIN_J7
SW[6] , PIN_H7
SW[7] , PIN_E3
SW[8] , PIN_E4
SW[9] , PIN_D2
增量器等效RTL
•注意观察,这个ROM实际是使用SYNC_RAM来实现的,这是一种能够初始化的同步RAM。
•再观察RAM的输入接口,除了读地址信号有效之外,其写使能信号、时钟等信号被置0
•另外RAM的后级接了一个D触収器
•注意:RTLview仅仅是一种“等效时序”概念上的结构,丌是真正结构。
•Tech Map View 中是真正使用的资源
•注意其中的RAM输出是丌带D触収器的
•反而是输入地址上带有D触収器。
•注意理解“时序等效”的电路结构,这一要点
学生实验一
问题解答
拨动开关观察不同频率的正弦波,得到的正弦波频率与计数器增量值的对应关系是?
答:随着计数值的增加,正弦波频率也增加
其中能得到的最低频率的正弦波是多少?设该频率为 f1
答:正弦波信号一个周期采样128点,电路的工作时钟为50MHz,即是采样周期为0.02s
所以
f
1
=
1
128
×
0.02
×
10
−
6
=
0.39
M
H
z
f1 = \frac{1}{{128 \times 0.02 \times {{10}^{ - 6}}}} = 0.39MHz
f1=128×0.02×10−61=0.39MHz
能有什么方法得到比F1频率还低的正弦波 ?
答:增加计数值
学生实验二
设计要求:
修改电路,把计数器的计数值和输入的计数增量信号都改为9比特,计数值的高7位连接ROM的地址线,低2位悬空。如上图所示。
–把9比特的计数器增量输入信号连接到9个拨码开关上
设输出正弦波频率为f1,电路系统时钟为fsys,计数器步进增量为CNT
f
1
=
C
N
T
2
N
×
f
s
y
s
f1 = \frac{{CNT}}{{{2^N}}} \times fsys
f1=2NCNT×fsys
能得到的最低频率的正弦波是多少?
f
1
=
1
1024
×
0.02
×
10
−
6
=
0.049
M
H
z
f1 = \frac{1}{{1024 \times 0.02 \times {{10}^{ - 6}}}} = 0.049MHz
f1=1024×0.02×10−61=0.049MHz