文章目录
- 1 老贺第一次课
- 2 high-level synthesis using vivado HLS
- 3 embedded system design flow on zynq using vivado
1 老贺第一次课
1.1 FPGA发展历史
1.2 FPGA基本结构
可编程逻辑器件(PLD)的种类
- CPLD(Complex Programmable Logic Device):多个PLA组成,基于乘积项技术,EEPROM/FLASH工艺。
- FPGA(Field Programmable Gate Array):实现LUT,SRAM工艺
- 复杂组合逻辑:CPLD;复杂时序逻辑:FPGA
- 快速通道互连
- 逻辑单元
- 逻辑阵列块
1.3 FPGA基本设计流程
- 设计导入/RTL实现
- RTL仿真
- 综合:得到网表
- 布局布线:implement
- 时序分析
- 门级仿真
- 板级模拟/测试
2 high-level synthesis using vivado HLS
2.1 introduction to high-level synthesis
HLS设计流程
- create project
- run C simulation
- synthesize
- run C/RTL co-simulation
- export RTL,封装成IP
vivado hls supports C/C++, systemC, opencl api and opencv
two step to verigying the design: C validation and RTL verification
对于testbench使用宏:可以避免代码被综合
#ifndef __SYNTHESIS__
#endif
RTL verification最好可以重复利用C testbench,RTL verification通过如果main函数返回值是0
2.2 improving performance
2.2.1 improving latency
2.2.2 improving throughput
2.2.3 performance bottleneck
2.3 data types(不考)
there are 4 data types in HLS
- standard C/C++ type
- apint: 面向C
- 只能用apcc来仿真,还没有debugger support
- ap_int/ap_fixed: 面向C++
g++和 Microsoft Visual Studio Compiler都可以编译 - systemC types
2.3 improving area and resources utillzation
2.4 handling block and ports level protocols(不考)
The arguments of the top-level function must be transformed to hardware interfaces with an IO protocol
block level protocols
port level protocols
2.5 coding consideration(不考)
3 embedded system design flow on zynq using vivado
3.1 introduction to embedded system design using zynq and vivado
- 双核 ARM A9 处理器
- AXI总线
- PS: processing system
APU: application processing unit - PL: programmable logic
3.2 extending the embedded system into PL
3.3 adding your own peripheral
AXI4 transactions
- AXI4-lite slave
- AXI4-lite master
- AXI4 slave/master
3.4 software deelopment environment
profile:配置文件
3.5 software development and debug(不考)
timer
- private timer: (standalone): 默认32-bit count down timer
- triple timer counter
- AXI timer