System Control Units (SCU) | ||||||||
---|---|---|---|---|---|---|---|---|
Reset Status Register | ||||||||
RSTSTAT Reset Status Register 31 30 29 28 | 27 | 26 | 25 | (0050H) 24 23 | 22 | 21 | 20 | Reset Value: Table 248 19 18 17 16 |
0 | LBTER M | LBPO RST | STBYR | HSMA | HSMS | SWD | EVR33 | EVRC | R22 | R21 | CB3 | CB1 | CB0 | 0 | PORS T |
---|
r rh rh rh rh rh rh rh rh rX rX rh rh rh r rh
r rh rh rh rh rh rh rh rh r rh rh
Field | Bits | Type | Description |
ESR0 | 0 | rh | Reset Request Trigger Reset Status for ESR0 0B The last reset was not requested by this reset trigger 1B The last reset was requested by this reset trigger |
ESR1 | 1 | rh | Reset Request Trigger Reset Status for ESR1 0B The last reset was not requested by this reset trigger 1B The last reset was requested by this reset trigger |
SMU | 3 | rh | Reset Request Trigger Reset Status for SMU (See SMU section for SMU trigger sources, including Watchdog Timers) 0B The last reset was not requested by this reset trigger 1B The last reset was requested by this reset trigger |
SW | 4 | rh | Reset Request Trigger Reset Status for SW 0B The last reset was not requested by this reset trigger 1B The last reset was requested by this reset trigger |
STM0 | 5 | rh | Reset Request Trigger Reset Status for STM0 Compare Match 0B The last reset was not requested by this reset trigger 1B The last reset was requested by this reset trigger |
STM1 | 6 | rh | Reset Request Trigger Reset Status for STM1 Compare Match (If Product has STM1) 0B The last reset was not requested by this reset trigger 1B The last reset was requested by this reset trigger |
STM2 | 7 | rh | Reset Request Trigger Reset Status for STM2 Compare Match (If Product has STM2) 0B The last reset was not requested by this reset trigger 1B The last reset was requested by this reset trigger |
STM3 | 8 | rh | Reset Request Trigger Reset Status for STM3 Compare Match (If Product has STM3) 0B The last reset was not requested by this reset trigger 1B The last reset was requested by this reset trigger |
User’s Manual 9-11 V1.5.0 SCUV2.1.25 2020-04
System Control Units (SCU)
Field | Bits | Type | Description |
STM4 | 9 | rh | Reset Request Trigger Reset Status for STM4 Compare Match (If Product has STM4) 0B The last reset was not requested by this reset trigger 1B The last reset was requested by this reset trigger |
STM5 | 10 | rh | Reset Request Trigger Reset Status for STM5 Compare Match (If Product has STM5) 0B The last reset was not requested by this reset trigger 1B The last reset was requested by this reset trigger |
PORST | 16 | rh | Reset Request Trigger Reset Status for PORST This bit is also set if the bits CB0, CB1, and CB3 are set in parallel. 0B This reset trigger has not occurred since the last clear (by RSTCON2.CLRC) 1B This reset trigger has occurred since the last clear (by RSTCON2.CLRC) |
CB0 | 18 | rh | Reset Request Trigger Reset Status for Cerberus System Reset 0B The last reset was not requested by this reset trigger 1B The last reset was requested by this reset trigger |
CB1 | 19 | rh | Reset Request Trigger Reset Status for Cerberus Debug Reset 0B The last reset was not requested by this reset trigger 1B The last reset was requested by this reset trigger |
CB3 | 20 | rh | Reset Request Trigger Reset Status for Cerberus Application Reset 0B The last reset was not requested by this reset trigger 1B The last reset was requested by this reset trigger |
R21 | 21 | rX | Reserved - 0 Read as 0; should be written with 0. |
R22 | 22 | rX | Reserved - 0 Read as 0; should be written with 0. |
EVRC | 23 | rh | Reset Request Trigger Reset Status for EVRC 0B This reset trigger has not occurred since the last clear (by RSTCON2.CLRC) 1B This reset trigger has occurred since the last clear (by RSTCON2.CLRC) |
EVR33 | 24 | rh | Reset Request Trigger Reset Status for EVR33 0B This reset trigger has not occurred since the last clear (by RSTCON2.CLRC) 1B This reset trigger has occurred since the last clear (by RSTCON2.CLRC) |
SWD | 25 | rh | Reset Request Trigger Reset Status for Supply Watchdog (SWD) The Supply Watchdog trigger is described in Power Management Controller “Supply Monitoring” chapter 0B This reset trigger has not occurred since the last clear (by RSTCON2.CLRC) 1B This reset trigger has occurred since the last clear (by RSTCON2.CLRC) |
User’s Manual 9-12 V1.5.0 SCUV2.1.25 2020-04
System Control Units (SCU)
Field | Bits | Type | Description |
HSMS | 26 | rh | Reset Request Trigger Reset Status for HSM System Reset (HSM S) 0B The last reset was not requested by this reset trigger 1B The last reset was requested by this reset trigger |
HSMA | 27 | rh | Reset Request Trigger Reset Status for HSM Application Reset (HSM A) 0B The last reset was not requested by this reset trigger 1B The last reset was requested by this reset trigger |
STBYR | 28 | rh | Reset Request Trigger Reset Status for Standby Regulator Watchdog (STBYR) 0B This reset trigger has not occurred since the last clear (by RSTCON2.CLRC) 1B This reset trigger has occurred since the last clear (by RSTCON2.CLRC) |
LBPORST | 29 | rh | LBIST termination due to PORST This bitfield indicates if the LBIST was early terminated due to the occurrence of a Power On Reset. If the status of this bitfield is 0, the application must still check the LBTERM to check if the LBIST was terminated properly. This bitfield is cleared when the RSTCON2.CLRC is set. 0B LBIST was not terminated early due to a Power On Reset 1B LBIST early termination due to the occurrence of Power On Reset |
LBTERM | 30 | rh | LBIST was properly terminated This bitfield indicates if the LBIST was terminated properly. This bitfield is cleared when the RSTCON2.CLRC is set. 0B LBIST was not terminated properly 1B LBIST was terminated properly |
0 | 2, 15:11, 17, 31 | r | Reserved Read as 0; should be written with 0. |
Table 248 Reset Values of RSTSTAT
Reset Type | Reset Value | Note |
---|---|---|
Cold PowerOn Reset | 0XX1 0000H | RSTSTAT |
Cold PowerOn Reset | 1001 0000H | RSTSTAT (Triggered by LVD Reset) |
User’s Manual 9-13 V1.5.0 SCUV2.1.25 2020-04