HDL日志(3)

toomay_Lee

已于 2023-06-26 22:42:00 修改

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文章标签： fpga开发

于 2023-06-24 22:44:41 首次发布

本文链接：https://blog.csdn.net/toomay_Lee/article/details/131367653

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本文展示了几个数字逻辑设计的例子，包括不同类型的移位寄存器（4-bit、5-bit、3-bit和32-bitLFSR），左右旋转寄存器，算术左/右移位寄存器以及多路复用DFF和3-input查找表（LUT）。这些模块在数字系统中常用于数据处理和存储。

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4-bit shift register

module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 
    always @(posedge clk or posedge areset)
        begin
            if(areset) q<=4'd0;
            else
                begin
                    if(load) q<=data;
                    else
                        begin
                            if(ena)
                                q<={1'd0,q[3:1]};
                        end
                end
        end
endmodule

Left/right retator

module top_module(
    input clk,
    input load,
    input [1:0] ena,
    input [99:0] data,
    output reg [99:0] q); 
    always @(posedge clk)
        begin
            if(load) q<=data;
            else
                begin
            		case(ena)
                		2'b01: q<={q[0],q[99:1]};
                        2'b10: q<={q[98:0],q[99]};
                        default:q<=q;
                    endcase
                end
        end
endmodule

Left/right arithmetic shift by 1 or 8

module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q); 
    
    always @(posedge clk)begin
        if(load)begin
            q <= data;
        end
        else begin
            if(ena)begin
                case(amount)
                    2'b00: q <= {q[62:0],1'b0};
                    2'b01: q <= {q[55:0],8'b0};
                    2'b10: q <= {q[63],q[63:1]};
                    2'b11: q <= {{8{q[63]}},q[63:8]};
                endcase
            end
            else begin
                q <= q;
            end
        end
    end

endmodule

5-bit LFSR

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 5'h1
    output [4:0] q
); 
    always @(posedge clk)
        begin
            if(reset) q<=5'h1;
            else
                q<={q[0]^0,q[4],q[3]^q[0],q[2:1]};
        end
endmodule

3-bit LFSR

module top_module (
	input [2:0] SW,      // R
	input [1:0] KEY,     // L and clk
	output [2:0] LEDR);  // Q
    always @(posedge KEY[0])
        begin
            LEDR<={KEY[1]?SW[2]:LEDR[1]^LEDR[2],KEY[1]?SW[1]:LEDR[0],KEY[1]?SW[0]:LEDR[2]};
        end
endmodule

32-bit LFSR

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 32'h1
    output [31:0] q
); 
    always @(posedge clk)
        begin
            if(reset) q<=32'h1;
            else
                q<={1'b0^q[0],q[31:23],q[22]^q[0],q[21:3],q[2]^q[0],q[1]^q[0]};
        end
endmodule

Shift register

module top_module (
    input clk,
    input resetn,   // synchronous reset
    input in,
    output out);
    reg q0,q1,q2;
    always @(posedge clk)
        begin
            if(!resetn) begin
                q0<=1'b0;
            	q1<=1'b0;
            	q2<=1'b0;
                out<=1'b0;
            end
            else
                begin
                    q0<=in;
            		q1<=q0;
            		q2<=q1;
            		out<=q2;
                end
        end
endmodule

module top_module (
	input clk,
	input resetn,
	input in,
	output out
);

	reg [3:0] sr;
	
	// Create a shift register named sr. It shifts in "in".
	always @(posedge clk) begin
		if (~resetn)		// Synchronous active-low reset
			sr <= 0;
		else 
			sr <= {sr[2:0], in};
	end
	
	assign out = sr[3];		// Output the final bit (sr[3])

endmodule

Shift register

module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output [3:0] LEDR
); //
    MUXDFF d1 (.KEY(KEY),.w(KEY[3]),.sw(SW[3]),.q(LEDR[3]));
    MUXDFF d2 (.KEY(KEY),.w(LEDR[3]),.sw(SW[2]),.q(LEDR[2]));
    MUXDFF d3 (.KEY(KEY),.w(LEDR[2]),.sw(SW[1]),.q(LEDR[1]));
    MUXDFF d4 (.KEY(KEY),.w(LEDR[1]),.sw(SW[0]),.q(LEDR[0]));
endmodule

module MUXDFF (input [3:0] KEY,input w,input sw,output q);
wire q1,q2;
    assign q1 = KEY[1]?w:q;
    assign q2 = KEY[2]?sw:q1;
    always @(posedge KEY[0])
        begin
            q<=q2;
        end
endmodule

3-input LUT

module top_module (
    input clk,
    input enable,
    input S,
    input A, B, C,
    output Z ); 
    reg [7:0] Q;
    always @(posedge clk)
        begin
            if(enable) Q<={Q[6:0],S};
            else Q<=Q;
        end
    assign Z = Q[{A,B,C}];
endmodule