HDL-More circuits

toomay_Lee

已于 2023-06-27 23:07:12 修改

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文章标签： fpga开发

于 2023-06-27 19:22:17 首次发布

本文链接：https://blog.csdn.net/toomay_Lee/article/details/131423628

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该文描述了三种不同的Verilog代码实现方式，用于在每次时钟上升沿时，根据Rule90规则更新一位全加器（DFF）阵列的状态。当加载信号有效时，DFFs被赋予输入数据；否则，每个DFF的输出是其相邻位的异或，模拟了一个位移并带有边界条件的逻辑操作。

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Rule 90

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q );
    integer i;
    always @(posedge clk)
        begin
            if(load) q<=data;
            else
                begin
                    q[0]<=(0^q[0])^(q[0]^q[1]);
                    for(i=1;i<511;i++)
                        begin
                            q[i]<=(q[i-1]^q[i])^(q[i]^q[i+1]);
                        end
                    q[511]<=(q[510]^q[511])^(q[511]^0);
                end
        end
endmodule

module top_module(
	input clk,
	input load,
	input [511:0] data,
	output reg [511:0] q);
	
	always @(posedge clk) begin
		if (load)
			q <= data;	// Load the DFFs with a value.
		else begin
			// At each clock, the DFF storing each bit position becomes the XOR of its left neighbour
			// and its right neighbour. Since the operation is the same for every
			// bit position, it can be written as a single operation on vectors.
			// The shifts are accomplished using part select and concatenation operators.
			
			//     left           right
			//  neighbour       neighbour
			q <= q[511:1] ^ {q[510:0], 1'b0} ;
		end
	end
endmodule

module top_module(
    input clk,
    input load,
    input [511:0] data,
    output [511:0] q
); 
    integer i;
    always @(posedge clk)
        begin
            if(load) q<=data;
            else
                begin
                    q[0]<=q[0]|~q[0]&q[1];
                    for(i=1;i<511;i++)
                        begin
                            q[i]<=~q[i]&q[i+1]|q[i]&(~q[i+1]|~q[i-1]);;
                        end
                    q[511]<=1;
                end
        end  
endmodule