HDL日志(2)

Four-bit binary counter

module top_module (
    input clk,
    input reset,      // Synchronous active-high reset
    output [3:0] q);
    always @(posedge clk)
        begin
            if(reset) q<=0;
            else
                begin
                    q<=q+1;
                end
        end
endmodule

Decade counter

module top_module (
    input clk,
    input reset,        // Synchronous active-high reset
    output [3:0] q);
    always @(posedge clk)
        begin
            if(reset)
                q<=0;
            else
                begin
                    if(q==9) q<=0;
                    else q<=q+1;
                end
        end
endmodule

Decade counter again

module top_module (
    input clk,
    input reset,
    output [3:0] q);
    always @(posedge clk)
        begin
            if(reset) q<=1;
            else
                begin
                    if(q==10) q<=1;
                    else q<=q+1;
                end
        end
endmodule

Slow decade counter

module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);
    always @(posedge clk)
        begin
            if(reset) q<=0;
            else
                begin
                    if(q==9) 
                        begin
                            if(slowena)
                            q<=0;
                        end
                    else
                        begin
                            if(slowena)
                                q<=q+1;
                        end
                end
        end
endmodule

Counter 1-12

module top_module (
    input clk,
    input reset,
    input enable,
    output [3:0] Q,
    output c_enable,
    output c_load,
    output [3:0] c_d
); //
	assign c_enable = enable;
    count4 the_counter (clk, c_enable, c_load, c_d, Q);
    assign c_load = reset|(Q==4'hc&&enable==1);
    assign c_d = c_load?1'b1:1'b0;
endmodule

Counter 100

module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
); //
    reg[3:0] q1,q2,q3;
    assign c_enable = {q1==4'd9&&q2==4'd9,q1==4'd9,1'b1};
    bcdcount counter0 (clk, reset, c_enable[0], q1);
    bcdcount counter1 (clk, reset, c_enable[1], q2);
    bcdcount counter2 (clk, reset, c_enable[2], q3);
    assign OneHertz = q1==4'd9&&q2==4'd9&&q3==4'd9;
endmodule

assign 连续赋值语句并行关系，与位置顺序无关。

4-digit decimal counter

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    output [3:1] ena,
    output [15:0] q);
    assign ena = {(q[11:8]==4'd9&&q[7:4]==4'd9&&q[3:0]==4'd9),q[7:4]==4'd9&&q[3:0]==4'd9,q[3:0]==4'd9};
    integer i;
    always @(posedge clk)
        begin
            if(reset) q<=0;
            else
                begin
                    if(q[3:0]==4'd9) q[3:0]<=0;
                    else q[3:0]<=q[3:0]+1;
                    if(q[7:4]==4'd9)begin if(ena[1]==1)q[7:4]<=0;end
                    else if(ena[1]==1) q[7:4]<=q[7:4]+1;
                    if(q[11:8]==4'd9&&ena[2]==1) q[11:8]<=0;
                    else if(ena[2]==1) q[11:8]<=q[11:8]+1;
                    if(q[15:12]==4'd9&&ena[3]==1) q[15:12]<=0;
                    else if(ena[3]==1) q[15:12]<=q[15:12]+1;
                end
        end
endmodule

module top_module (
    input clk,
    input reset,   // Synchronous active-high reset
    output [3:1] ena,
    output [15:0] q);
    assign ena = {(q[11:8]==4'd9&&q[7:4]==4'd9&&q[3:0]==4'd9),q[7:4]==4'd9&&q[3:0]==4'd9,q[3:0]==4'd9};
    integer i;
    always @(posedge clk)
        begin
            if(reset) q<=0;
            else
                begin
                    if(q[3:0]==4'd9) q[3:0]<=0;
                    else q[3:0]<=q[3:0]+1;
                    for(i = 2; i<5;i++)
                        begin
                            if(q[(4*i-4)+:4]==4'd9&&ena[i-1]==1) q[(4*i-4)+:4]<=0; //不支持这种写法Data_i[i*8-1:i*8-8]，下标中不能有变量，除非Data_i[(i*8-8)+:8]，表示从 i*8-8 这位开始，向高数8位。
                            else
                                begin
                                    if(ena[i-1]==1) q[(4*i-4)+:4]<= q[(4*i-4)+:4]+1;
                                end
                        end
                end
        end
endmodule