主机控制器接口(Host Controller Interface): HCI

最新推荐文章于 2023-07-26 14:08:08 发布
最新推荐文章于 2023-07-26 14:08:08 发布
阅读量492 收藏
点赞数
分类专栏： 蓝牙5.3 文章标签： 蓝牙
版权声明：本文为博主原创文章，遵循 CC 4.0 BY-SA 版权协议，转载请附上原文出处链接和本声明。
本文链接：https://blog.csdn.net/u011310383/article/details/120680748
版权

目录

介绍

在这里插入图片描述
在这里插入图片描述

HCI数据格式

ID和句柄

HCI命令和事件中有2类标识符.
ID, 由主机分配, 在两端设备使用, 并在PDU中发送.

句柄, 由主机在命令中分配或控制器在事件中分配, 是主机和控制器之间的标识符.
一些句柄共享相同的数字空间, 其他句柄则有独立的数字空间.

当一个设备为新对象分配ID或句柄时, 不允许使用当前数字空间当前分配给其他对象的句柄.

当一个设备删除ID或句柄时, 它可以重用ID或句柄.

HCI特定信息交换

主机控制器传输层提供HCI特定信息的透明交换.
这些传输机制提供这些能力, 主机发送HCI命令,接受HCI事件, 和发送数据给控制器.
因为主机控制器传输层体统HCI特性信息的透明交换, HCI规范指明主机和控制器间命令,
事件和数据交换的格式.

HCI命令包

HCI命令包用来从主机发命令到控制器.
在这里插入图片描述

HCI ACL数据包

HCI ACL数据包用来在主机与控制器间交换数据.
有2种类型的HCI ACL数据包:

  • Automatically-Flushable
  • Non-Automatically-Flushable

Automatically-Flushable 数据包基于自动刷新时间会被刷新.
Non-Automatically-Flushable 数据包不受自动刷新时间控制且不能被自动刷新.

在这里插入图片描述

HCI同步数据包

HCI事件包

HCI时间包被控制器用来通知主机事件的发生.
在这里插入图片描述

HCI ISO数据包

控制器句柄

Connection_Handles, Sync_Handles, Advertising_Handles,和BIG_Handles
是用来标识主机和控制器之间逻辑通道的控制器句柄.

Connection_Handles是由主机控制器分配,当一个新的逻辑传输被创建或保留并且
报告主句以下事件发生: 连接完成, 同步连接完成, LE 连接完成, LE增强连接完成,
LE CIS请求, LE创建BIG完成, HCI_LE_BIG_Sync_Established, 或命令完成事件跟在
LE Set CIG Parameters命令之后.

Advertising_Handles是由主机分配,当一个新的 advertising set被LE Set Extended Advertising Parameters命令创建.

Sync_Handles由控制器分配, 当一个新的逻辑传输被创建并且在 LE Periodic Advertising Sync
Established event事件中报告给主机.

BIG_Handles 由主机分配,当BIG被以下命令创建时:
LE Create BIG, LE Create BIG Test, and LE_BIG_Create_Sync.

所有由控制器分配的连接句柄应该从相同的数字空间获取.
Sync handles可以由控制器在不同的数字空间分配.
Advertising handles和BIG handles由主机在不同的数字空间分配.

HCI 配置参数

最低0.47元/天 解锁文章
hello可乐
关注
  • 0
    点赞
  • 踩
  • 0
    收藏
    觉得还不错? 一键收藏
  • 0
    评论
专栏目录
Host controller interface(HCI)
ggbondg的专栏
03-22 2689
Host controller interfaceFrom Wikipedia, the free encyclopediaA host controller interface (HCI) is a register level interface which allows a host controller for USB or FireWire to communicate with
Host/Controller Interface (HCI)
yinghuihong的专栏
06-26 1329
•Reused from standard Bluetooth specification, with new additional commands for low energy-specific functions •Thin layer; doesn‟t perform any processing 轻层，不执行任何处理 •In a dual-chip solution (with se
蓝牙Host Controller Interface笔记
夜影轩的专栏
05-05 2991
1.概述     HCI提供了一个统一的使用蓝牙控制器（BR/EDR Controller，BR/EDR/LE Controller，LE Controller，AMP Controller等）的方法，它屏蔽了蓝牙的基带部分，提供了统一的数据进入基带的方法。     首先，蓝牙的BaseBand部分有以下几种控制器： • BR/EDR Controller • BR/EDR/LE Co
Universal Host Controller Interface (UHCI)
03-04
Universal Host Controller Interface (UHCI)<br>Design Guide<br><br>找了很久没看到uhci spec，没解禁的东西真难啊
主机控制器接口（HCI）
weixin_30457551的博客
04-19 403
主机控制器接口（HCI）提供了一种访问蓝牙硬件能力的通用接口。 HCI固件通过访问基带命令、链路管理器命令、硬件状态寄存器、控制寄存器以及事件寄存器实现对蓝牙硬件的HCI命令。 HCI是通过包的方式来传送数据、命令和事件的，所有在主机和主机控制器之间的通信都以包的形式进行。包括每个命令的返回参数都通过特定的事件包来传输。HCI有数据、命令和事件三种包，其中数据包是双向的，命令包只能从主机发往主...
Enhanced Host Controller Interface
04-29
The Enhanced Host Controller Interface (EHCI) specification describes the register-level interface for a Host Controller for the Universal Serial Bus (USB) Revision 2.0. The specification includes a description of the hardware/software interface between system software and the host controller hardware.
USB主机控制器接口协议
10-04
USB核心协议定义了主机控制...而主机控制器接口（Host Controller Interface， HCI）目前形成了两种规范，Enhanced HCI和Open HCI。 本资源包含了EHCI和OHCI的规范，为进行HCI层设计以及调试的朋友们提供不错的参考。
基于OHCI 的主机控制器的接口设计
10-19
本文主要探讨的是基于OHCI（Open Host Controller Interface）的USB主机控制器接口设计，这是一种在嵌入式系统中广泛应用的USB主机控制器接口规范。OHCI规范由Compaq、Microsoft等公司制定，旨在提供一种标准化的...
采用单片无操作系统的USB主机控制器接口设计
10-19
USB体系结构包括多个层次的硬件层，其中主机控制器接口（Host Controller Interface, HCI）是关键部分。在嵌入式系统中，用户程序和设备驱动通过URB（Universal Request Block）与主机控制器交互。URB包含了如设备...
蓝牙主控制器接口简析
12-08
蓝牙主控制器接口（HCI，Host Controller Interface）是蓝牙技术中一个关键的接口规范，它定义了主机（Host）与蓝牙控制器（Controller）之间的通信方式。HCI允许上层软件（如链路管理器、逻辑链路控制和适应协议等...
HCI接口协议.rar
06-12
The present document specifies a logical interface that enables contactless applications hosted on the UICC. The present document covers the configuration where the one host is embedded in the UICC which is connected to the hostcontroller embedded in the CLF.
Open Host Controller Interface Specification
03-04
TABLE OF CONTENTS<br>1. INTRODUCTION.........................................................................................................1<br>2. TERMS AND ABBREVIATIONS.................................................................................2<br>3. ARCHITECTURAL OVERVIEW..................................................................................6<br>3.1 Introduction..........................................................................................................6<br>3.2 Data Transfer Types............................................................................................7<br>3.3 Host Controller Interface.....................................................................................7<br>3.3.1 Communication Channels............................................................................................7<br>3.3.2 Data Structures...........................................................................................................8<br>3.4 Host Controller Driver Responsibilities...........................................................12<br>3.4.1 Host Controller Management....................................................................................12<br>3.4.2 Bandwidth Allocation................................................................................................12<br>3.4.3 List Management......................................................................................................13<br>3.4.4 Root Hub..................................................................................................................13<br>3.5 Host Controller Responsibilities......................................................................13<br>3.5.1 USB States...............................................................................................................13<br>3.5.2 Frame management...................................................................................................14<br>3.5.3 List Processing..........................................................................................................14<br>4. DATA STRUCTURES...............................................................................................15<br>4.1 Overview.............................................................................................................15<br>4.2 Endpoint Descriptor..........................................................................................16<br>4.2.1 Endpoint Descriptor Format......................................................................................16<br>4.2.2 Endpoint Descriptor Field Definitions........................................................................17<br>4.2.3 Endpoint Descriptor Description...............................................................................18<br>4.3 Transfer Descriptors.........................................................................................19<br>4.3.1 General Transfer Descriptor......................................................................................19<br>4.3.1.1 General Transfer Descriptor Format...................................................................20<br>4.3.1.2 General Transfer Descriptor Field Definitions.....................................................20<br>4.3.1.3 General Transfer Descriptor Description.............................................................21<br>4.3.1.3.1 Buffer Address Determination.....................................................................21<br>4.3.1.3.2 Packet Size..................................................................................................21<br>4.3.1.3.3 Condition Codes..........................................................................................22<br>4.3.1.3.4 Sequence Bits..............................................................................................22<br>4.3.1.3.5 Transfer Completion....................................................................................23<br>4.3.1.3.6 Transfer Errors............................................................................................23<br>4.3.1.3.6.1 Transmission Errors..............................................................................24<br>4.3.1.3.6.2 Sequence Errors...................................................................................24<br>vi<br><br>OpenHCI - Open Host Controller Interface Specification for USB<br>4.3.1.3.6.3 System Errors.......................................................................................25<br>4.3.1.3.7 Special Handling..........................................................................................25<br>4.3.1.3.7.1 NAK.....................................................................................................25<br>4.3.1.3.7.2 Stall......................................................................................................25<br>4.3.2 Isochronous Transfer Descriptor...............................................................................25<br>4.3.2.1 Isochronous Transfer Descriptor Format............................................................25<br>4.3.2.2 Isochronous Transfer Descriptor Field Definitions..............................................26<br>4.3.2.3 Isochronous Transfer Descriptor Description......................................................26<br>4.3.2.3.1 Buffer Addressing........................................................................................27<br>4.3.2.3.2 Data Packet Size.........................................................................................28<br>4.3.2.3.3 Status..........................................................................................................28<br>4.3.2.3.4 Transfer Completion....................................................................................28<br>4.3.2.3.5 Transfer Errors............................................................................................28<br>4.3.2.3.5.1 Transmission Errors..............................................................................29<br>4.3.2.3.5.2 Sequence Errors...................................................................................29<br>4.3.2.3.5.3 Time Errors..........................................................................................29<br>4.3.2.3.5.4 System Errors.......................................................................................30<br>4.3.2.3.6 Special Handling..........................................................................................31<br>4.3.2.3.6.1 NAK and STALL.................................................................................31<br>4.3.2.4 PacketStatusWord..............................................................................................31<br>4.3.2.4.1 Packet Status Word Field Definitions...........................................................31<br>4.3.3 Completion Codes.....................................................................................................32<br>4.3.3.1 Condition Code Description...............................................................................33<br>4.4 Host Controller Communications Area............................................................33<br>4.4.1 Host Controller Communications Area Format..........................................................34<br>4.4.2 Host Controller Communications Area Description...................................................34<br>4.4.2.1 HccaInterruptTable............................................................................................34<br>4.4.2.2 HccaFrameNumber............................................................................................35<br>4.4.2.3 HccaDoneHead..................................................................................................35<br>4.5 Endpoint List Processing.................................................................................36<br>4.6 Transfer Descriptor Queue Processing...........................................................37<br>5. HOST CONTROLLER DRIVER................................................................................38<br>5.1 Host Controller Management............................................................................38<br>5.1.1 Initialization..............................................................................................................38<br>5.1.1.1 Load and Locate................................................................................................39<br>5.1.1.2 Verify Host Controller and Allocate Resources...................................................39<br>5.1.1.3 Take Control of Host Controller.........................................................................40<br>5.1.1.3.1 SMM Driver, Power-Up..............................................................................40<br>5.1.1.3.2 BIOS Driver................................................................................................40<br>5.1.1.3.3 OS Driver, SMM Active..............................................................................41<br>5.1.1.3.4 OS Driver, BIOS Active..............................................................................41<br>5.1.1.3.5 OS Driver, neither SMM nor BIOS.............................................................41<br>5.1.1.3.6 SMM Driver, Re-Entry................................................................................42<br>vii<br><br>OpenHCI - Open Host Controller Interface Specification for USB<br>5.1.1.4 Setup Host Controller........................................................................................42<br>5.1.1.5 Begin Sending SOFs...........................................................................................42<br>5.1.2 Operational States.....................................................................................................43<br>5.1.2.1 USBRESET..........................................................................................................43<br>5.1.2.2 USBOPERATIONAL..............................................................................................43<br>5.1.2.3 USBSUSPEND......................................................................................................43<br>5.1.2.4 USBRESUME.......................................................................................................44<br>5.2 Schedule.............................................................................................................44<br>5.2.1 Sample Host Controller Driver Definitions................................................................46<br>5.2.2 Miscellaneous Definitions..........................................................................................46<br>5.2.3 Host Controller Descriptors Definitions.....................................................................47<br>5.2.4 Host Controller Driver Descriptor Definitions...........................................................48<br>5.2.5 Host Controller Endpoints........................................................................................50<br>5.2.6 Host Controller Driver Internal Definitions................................................................51<br>5.2.7 Endpoint Descriptor Lists.........................................................................................54<br>5.2.7.1 Bulk and Control................................................................................................54<br>5.2.7.1.1 Adding........................................................................................................54<br>5.2.7.1.2 Removing....................................................................................................56<br>5.2.7.1.3 Pause...........................................................................................................59<br>5.2.7.2 Interrupt.............................................................................................................61<br>5.2.7.2.1 Polling Rate.................................................................................................64<br>5.2.7.2.2 Adding........................................................................................................66<br>5.2.7.2.3 Removing....................................................................................................66<br>5.2.7.2.4 Pause...........................................................................................................67<br>5.2.7.3 Isochronous.......................................................................................................67<br>5.2.7.3.1 Adding........................................................................................................68<br>5.2.7.3.2 Removing....................................................................................................68<br>5.2.7.3.3 Pause...........................................................................................................68<br>5.2.8 Transfer Descriptor Queues......................................................................................68<br>5.2.8.1 The NULL or Empty Queue...............................................................................68<br>5.2.8.2 Adding to a Queue.............................................................................................69<br>5.2.8.3 Removing from a Queue.....................................................................................73<br>5.2.8.4 Cancel................................................................................................................74<br>5.2.9 Done Queue..............................................................................................................75<br>5.2.10 USB Bandwidth Allocation.....................................................................................78<br>5.2.10.1 Scheduling Overrun Errors...............................................................................78<br>5.2.11 ControlBulkServiceRatio........................................................................................79<br>5.3 Host Controller Interrupt...................................................................................80<br>5.4 FrameInterval Counter.......................................................................................85<br>5.5 Root Hub............................................................................................................86<br>viii<br><br>OpenHCI - Open Host Controller Interface Specification for USB<br>6. HOST CONTROLLER..............................................................................................87<br>6.1 Introduction........................................................................................................87<br>6.2 USB States.........................................................................................................87<br>6.2.1 UsbOperational.........................................................................................................88<br>6.2.2 UsbReset..................................................................................................................89<br>6.2.3 UsbSuspend..............................................................................................................89<br>6.2.4 UsbResume...............................................................................................................89<br>6.3 Frame Management...........................................................................................90<br>6.3.1 Frame Timing............................................................................................................90<br>6.3.2 StartOfFrame (SOF) Token Generation.....................................................................91<br>6.3.3 HccaFrameNumber Update.......................................................................................91<br>6.4 List Processing..................................................................................................92<br>6.4.1 Priority.....................................................................................................................92<br>6.4.1.1 List Priority........................................................................................................93<br>6.4.1.1.1 Periodic Lists...............................................................................................93<br>6.4.1.1.2 Nonperiodic Lists........................................................................................93<br>6.4.1.2 Endpoint Descriptor Priority..............................................................................94<br>6.4.1.3 Transfer Descriptor Priority................................................................................95<br>6.4.2 List Service Flow......................................................................................................95<br>6.4.2.1 List Enabled Check............................................................................................95<br>6.4.2.2 Locating Endpoint Descriptors...........................................................................97<br>6.4.3 Endpoint Descriptor Processing................................................................................98<br>6.4.4 Transfer Descriptor Processing.................................................................................99<br>6.4.4.1 Isochronous Relative Frame Number Calculation................................................99<br>6.4.4.2 Packet Address and Size Calculation..................................................................99<br>6.4.4.3 Packet Transfer Time Check.............................................................................101<br>6.4.4.4 Largest Data Packet Counter Operation...........................................................102<br>6.4.4.5 Status Writeback..............................................................................................102<br>6.4.4.5.1 General Transfer Descriptor Status Writeback...........................................102<br>6.4.4.5.2 Isochronous Transfer Descriptor Status Writeback....................................103<br>6.4.4.6 Transfer Descriptor Retirement........................................................................103<br>6.4.5 Done Queue............................................................................................................104<br>6.4.5.1 Done Queue Interrupt Counter.........................................................................104<br>6.5 Interrupt Processing........................................................................................105<br>6.5.1 SchedulingOverrun Event........................................................................................105<br>6.5.2 WritebackDoneHead Event.....................................................................................106<br>6.5.3 StartOfFrame Event................................................................................................106<br>6.5.4 ResumeDetected Event...........................................................................................106<br>6.5.5 UnrecoverableError Event......................................................................................106<br>6.5.6 FrameNumberOverflow Event.................................................................................106<br>6.5.7 RootHubStatusChange Event..................................................................................107<br>6.5.8 OwnershipChange Event.........................................................................................107<br>ix<br><br>OpenHCI - Open Host Controller Interface Specification for USB<br>6.6 Root Hub..........................................................................................................107<br>7. OPERATIONAL REGISTERS.................................................................................108<br>7.1 The Control and Status Partition....................................................................109<br>7.1.1 HcRevision Register................................................................................................109<br>7.1.2 HcControl Register.................................................................................................109<br>7.1.3 HcCommandStatus Register....................................................................................112<br>7.1.4 HcInterruptStatus Register......................................................................................113<br>7.1.5 HcInterruptEnable Register....................................................................................115<br>7.1.6 HcInterruptDisable Register...................................................................................116<br>7.2 Memory Pointer Partition................................................................................117<br>7.2.1 HcHCCA Register...................................................................................................117<br>7.2.2 HcPeriodCurrentED Register.................................................................................117<br>7.2.3 HcControlHeadED Register...................................................................................118<br>7.2.4 HcControlCurrentED Register................................................................................118<br>7.2.5 HcBulkHeadED Register........................................................................................119<br>7.2.6 HcBulkCurrentED Register.....................................................................................119<br>7.2.7 HcDoneHead Register............................................................................................120<br>7.3 Frame Counter Partition..................................................................................120<br>7.3.1 HcFmInterval Register............................................................................................120<br>7.3.2 HcFmRemaining Register.......................................................................................121<br>7.3.3 HcFmNumber Register...........................................................................................122<br>7.3.4 HcPeriodicStart Register........................................................................................122<br>7.3.5 HcLSThreshold Register.........................................................................................123<br>7.4 Root Hub Partition...........................................................................................123<br>7.4.1 HcRhDescriptorA Register......................................................................................124<br>7.4.2 HcRhDescriptorB Register......................................................................................125<br>7.4.3 HcRhStatus Register...............................................................................................126<br>7.4.4 HcRhPortStatus[1:NDP] Register...........................................................................128<br>APPENDIX A—PCI INTERFACE................................................................................132<br>PCI CONFIGURATION...............................................................................................132<br>PCI Configuration Spaces for OpenHCI-compliant USB Host Controller.........133<br>COMMAND Register.......................................................................................................134<br>CLASS_CODE Register...................................................................................................134<br>BAR_OHCI Register........................................................................................................135<br>x<br><br>OpenHCI - Open Host Controller Interface Specification for USB<br>APPENDIX B—LEGACY SUPPORT INTERFACE SPECIFICATION........................136<br>OVERVIEW.................................................................................................................136<br>OPERATIONAL THEORY..........................................................................................137<br>Keyboard/Mouse Input..........................................................................................137<br>Keyboard Output...................................................................................................138<br>Emulation Interrupts..............................................................................................138<br>Mixed Environment.........................................................................................................139<br>Gate A20 Sequence.........................................................................................................139<br>SYSTEM REQUIREMENTS........................................................................................140<br>Host Controller Mapping.......................................................................................140<br>SMI Signaling.........................................................................................................141<br>Intercept Port 60h and 64h Accesses..................................................................141<br>Interrupts................................................................................................................141<br>Run-time Memory ..................................................................................................141<br>PROGRAMMING INTERFACE...................................................................................142<br>Modifications to existing registers......................................................................142<br>HcRevision Register........................................................................................................142<br>Legacy Support Registers....................................................................................142<br>HceInput Register............................................................................................................143<br>HceOutput Register.........................................................................................................143<br>HceStatus Register...........................................................................................................144<br>HceControl Register........................................................................................................145<br>IMPLEMENTATION NOTES.......................................................................................146<br>Emulation Interrupt Decode..................................................................................146<br>A20 Gate.................................................................................................................146
基于OHCI的嵌入式USB主机控制器接口实现
10-19
【基于OHCI的嵌入式USB主机控制器接口实现】这篇论文主要探讨了如何在嵌入式系统中开发和实现USB主机控制器接口，特别是在S3C2410平台上。USB体系结构包括硬件层和软件层，其中主机控制器驱动程序（HCD）扮演着关键...
主机控制器接口(Host Controller Interface): 3线UART传输层
技术学习
10-05 290
蓝牙5.3: 3线UART传输层
主机控制器接口(Host Controller Interface): UART传输层
技术学习
10-05 554
蓝牙5.3: UART传输层
主机控制器接口(Host Controller Interface): USB传输层
技术学习
10-05 273
蓝牙5.3: USB传输层
HOST CONTROLLER INTERFACE FUNCTIONAL SPECIFICATION
kikyo_yu的博客
11-04 407
HCI提供了一套到CONTROLLER命令接口。 HCI Command packet: HCI ACL Data packet: HCI Event packet: 开启controller： 2018/10/31 18:18:51.148812    Command    0x0c03    Ctrl/BB    Reset            1           ...
USB主机控制器(Host Controller)--深入理解
最新发布
qq_37391577的博客
07-26 1287
USB 设备和主机的接口就是host controller，一个主机可以支持多个host controller，比如分别属于不同厂商的。USB host controller的作用：控制所有的USB设备的通信。CPU把要做的事情分配给主机控制器，然后自己想干什么就干什么去，主机控制器替他去完成剩下的事情，事情办完了再通知CPU。否则让CPU去盯着每一个设备做每一件事情，那是不现实的。控制器的主要工作是什么?把数扔出去，把数拿回来。绝对不应该偷偷加工数据。
HCI （主机控制接口(Host Controller Interface)）
andywu24的专栏
10-16 2638
HCI，即主机控制接口，属于蓝牙协议栈的一部分。 主机控制接口属于蓝牙协议栈的一部分。 蓝牙规范包含了一个符合标准的接口定义（主机控制器接口），它适用于蓝牙通讯模块的硬件部分。此定义描述了位于HCI驱动程序（主机的一部分，也即蓝牙通讯模块的使用者）和主机控制器固件（蓝牙通讯模块本身的一部分）之间的接口。
中文 Open Host Controller Interface Specification for USB pdf
05-12
机翻中文，双语对照

“相关推荐”对你有帮助么？

  • 非常没帮助
  • 没帮助
  • 一般
  • 有帮助
  • 非常有帮助
提交
评论
添加红包

请填写红包祝福语或标题

个

红包个数最小为10个

元

红包金额最低5元

当前余额3.43元 前往充值 >
需支付：10.00元
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付元
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明：

1.余额是钱包充值的虚拟货币，按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载，可以购买VIP、付费专栏及课程。

余额充值