LPDDR4 Data Eye Training

3.1 Data Eye Training

3.1.1 Read Training

The DQS signal on the memory interface is bidirectional. The PHY in many (not all) memoryarchitectures will generate a DQS gate signal that switches the read DQS capture logic on and off -on for reads and off for writes. Gate training is the process of setting the timing of the read DQSgate to turn on prior to the first read DQS One way to do gate training, as discussed above, is to firstalign the rising edge of the gate signal to the rising edge of the first read DQS in a read burst. Oncethis alignment is know, the gate signal can be moved back far enough from the first read DQS toprovide necessary timing margin. There may be other ways to do gate training as well. The goal ofgate training is to locate the setting at which the initial read DQS rising edge aligns with the risingedge of the read DQS gate. Once this setting is identified, the read DQS gate can be adjusted to theapproximate midpoint of the read DQS preamble prior to the DQS.

3.1.2 Write Training

When the DQS is not aligned with the DQ training is happened for centre alignment. In memorydelay line is there to provide delay of tDQSDQ between DQS and DQ.For finding that delay thathow much delay memory is applying for finding that write training is required.

3.2 Write Levelling

The memory controller using the write levelling procedure must have adjustable delay settings on itsDQS strobe to align the rising edge of DQS to the clock at the DRAM pins. This is accomplishedwhen the DRAM asynchronously feeds back the CK status via the DQ bus and samples with therising edge of DQS. The controller repeatedly delays the DQS strobe until a CK transition from 0 to1 is detected. The DQS delay established by this procedure helps ensure tDQSS, tDSS, and tDSHspecifications in systems that use fly-by topology by de-skewing the trace length mismatch. Aconceptual timing of this procedure is shown in Write Levelling Concept

.3.3 CA Calibration

When memory training begins on a platform with poorly aligned Control, Clock andCommand/Address (CA) signals, even the most basic commands, such as Reset or entry into CATraining mode, might not register correctly in some of the DRAM devices. Current solutionsdemand very strict length matching and/or manual initial timing settings for all these signal types foreach problematic platform. As a result, much time and efforts can be spent for just enabling the mostbasic training routines to run.When command address is send by memory controller which is not International Journal of Recent Trends in Engineering & Research (IJRTER)Volume 03, Issue 06; June - 2017 [ISSN: 2455-1457]@IJRTER-2017, All Rights Reserved 226centred align with memory clock and chip select line is also not centre align with clock so forfinding the correct pattern which is accurately sent by controller that process is called CAcalibration.

3.4 DLL

A DLL can be used to change the phase of a clock signal (a signal with a periodic waveform),usually to enhance the clock rise-to-data output valid timing characteristics of integratedcircuits (such as DRAM devices). DLLs can also be used for clock recovery (CDR). From theoutside, a DLL can be seen as a negative-delay gate placed in the clock path of a digital circuit. Themain component of a DLL is a delay chain composed of many delay gates connected output-to-input.The input of the chain (and thus of the DLL) is connected to the clock that is to be negativelydelayed. A multiplexer is connected to each stage of the delay chain; the selector of this multiplexeris automatically updated by a control circuit to produce the negative delay effect. The output of theDLL is the resulting, negatively delayed clock signal.

ref：http://www.ijrter.com/papers/volume-3/issue-6/case-study-of-lpddr4-phy.pdf