EVMC6678L时钟主频配置

本文从两个方面来讲解如何配置6678的CPU：

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关于6678芯片时钟初始化可以利用F:\ProgramFiles\ti\ccsv8\ccs_base\emulation\boards\evmc6678l\gel 文件夹下面的GEL文件来进行初始化，在Target Configuration.ccxml下Advanced中右边Initialization script中加载6678的gel文件即可。

1. 打开GEL文件，第42行注释文件详细解释了CPU输出频率的计算，以及倍频器与分频器的设置：

​// The System PLL governs the device (CorePac) operating speed.  
//
// Each board designer defines the CLKIN frequency.  On the 
// TMDXEVM6678L,LE,LXE EVMs, the CLKIN frequency defined to 100MHz.  The 
// values for PLL1_M(39) and PLL1_D(1) defined below are pre-set 
// to provide a 1000MHz operating frequency on the EVMs.
//
// Other board designs using different CLKIN frequencies and/or 
// applications that requiring other operating frequecies, the PLL can 
// be configured by adjusting PLL1_M and PLL1_D per the 
// following formula:
//
//     Target Frequency (MHz) = 
//         input_clock (MHz) * [(PLL1_M + 1)]/ (2 * (PLL1_D + 1) )
//
// Table 2-13, "C66x DSP System PLL Configuration" in the device data sheet, 
// http://focus.ti.com/lit/ds/symlink/tms320c6678.pdf provides the suggested
// values for PLL1_M and PLL1_D for various input clocks and desired
// operating frequencies.
// 
// Please note that there might be multiple PLL1_M and PLL1_D
// values for the same Input clock and Desired Device Speed as long as the 
// multipliers and dividers are in the acceptable range. 
//
// More details on the PLL including the limitations on acceptable ranges
// for multipliers and dividers are in the PLL's user guide at
// http://www.ti.com/lit/sprugv2
// 
// The table provides some sample values of PLL1_M and PLL1_D:
//
// Please select PLL1_M values such that 0 < PLL1_M <= 64
// +--------------------+---------------+--------+--------+
// | (CLK)Desired       | (CLKIN) Input |        |        |
// | Device Speed (MHz) | Clock (MHz)   | PLL1_M | PLL1_D |
// +--------------------+---------------+--------+--------+
// | 1000               | 100           | 19     | 0      |
// | 1000               | 100 (EVM)     | 39     | 1      |
// | 1250               | 100           | 24     | 0      |
// | 1000               | 50            | 39     | 1      |
// | 1000               | 156.25        | 63     | 4      |
// +--------------------+---------------+--------+--------+
//
// +--------------------+---------------+--------+--------+
// | PA PLL VCO         | (CLKIN) Input |        |        |
// | Rate (MHz)         | Clock (MHz)   | PLL1_M | PLL1_D |
// +--------------------+---------------+--------+--------+
// | 1050               | 100.00 (EVM)  | 20     | 0      |
// | 1044               | 122.88        | 31     | 1      |
// | 1050               | 122.88        | 204    | 11     |
// | 1050               | 156.25        | 335    | 24     |
// +--------------------+---------------+--------+--------+
//
// +--------------------+---------------+--------+--------+
// | DDR3 PLL VCO       | (CLKIN) Input |        |        |
// | Rate (MHz)         | Clock (MHz)   | PLL1_M | PLL1_D |
// +--------------------+---------------+--------+--------+
// | 1333               | 66.667 (EVM)  | 19     | 0      |
// | 1066               | 66.667        | 31     | 1      |
// | 800                | 66.667        | 11     | 0      |
// +--------------------+---------------+--------+--------+​

从注释文件中可知，CPU的频率 = 输入时钟频率 * [(PLL1_M + 1)] / (2 * (PLL1_D + 1) )，例如当输入时钟频率（Input Clock）为100Mhz时，若设置PLL1_M为24，PLL1_D为0，则得到的输出时钟频率为1250MHZ。定位文件到第857行，

这里的Init_PLL函数为配置CPU时钟频率的入口函数，入口参数为倍频值，分频值，默认GEL文件中在第101行定义的为39，1：

#define PLL1_M 39  
#define PLL1_D 1


#define DDR3_BASE_ADDRESS            0x80000000

打开Init_PLL(int pll_mult, int pll_div )函数：

hotmenu Init_PLL(int pll_mult, int pll_div )
{
    int i, TEMP;
    /* Defa