arm学习笔记之nandflash

首先 不管学习哪一款芯片还是应该自己先去看该款芯片的datasheet。

这篇笔记是基于学习2440开发板的K9F2G08U0B 或K9F2G08B0B 芯片

正文：

计算nandflash的大小：

图上可以看到K9F2G08U0B   一页的大小 = 2K+64byte  其中64byte用来保存坏块、差错校验等等信息  。 一个块包涵64页。 一个芯片包含2048个块。所以就得出一个nandflash芯片总容量的计算公式   1 Device = (2K+64)B x 64Pages x 2,048 Blocks  = 2,112 Mbits

介绍比较重要的几个引脚：

CLE： COMMAND LATCH ENABLE （指令锁存使能）
The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal.

ALE ：ADDRESS LATCH ENABLE（地址锁使能）
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high

CE : CHIP ENABLE(片选)
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase operation.

RE : READ ENABLE(读使能)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the i nternal column address counter by one.

WE: WRITE ENABLE（写使能）
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse

WP : WRITE PROTECT(写保护)
The WP pin provides inadvertent program/erase protection during power transitions. The internal high volt-age generator is reset when the WP pin is active low  

R&B ： READY/BUSY OUTPUT（读写忙）
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.

上面的表格应该配合下面的时序图来看：  注意默认工作条件是3.3V 下

2440 nandflash 时序图：

有了K9F2G08U0B 时序图再对照2440手册的时序图 就可以确定2440 nandflash 最重要的三个控制器配置参数

TACLS=Tcls-Twp 表示地址锁存到WE 有效的时间；

TWRPH0：表示nWE/nRE持续的时间

TWRPH1：表示nWE无效到数据或地址无效的延时；（这里可以直接看成TDH）

对照上面的表格和2440的HCLK的时钟频率大概是100多兆赫兹（7ns左右） 可以将 NFCONF 中的 TACLS = 1； TWRPH0 = 1； TWRPH1 = 0；

但是为了稳定 可以把TWRPH0 设置为2 TWRPH1 设置为1； 延长一些时间。