hdlbits.01xz.net /Circuits/Sequential Logic/Finite State Machines/Lemmings2

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah ); 
    
    parameter LEFT = 4'b0001;
    parameter RIGHT = 4'b0010;
    parameter FALL_L = 4'b0100;
    parameter FALL_R = 4'b1000;
    
    reg [3:0] state, next;
    
    always @ (posedge clk, posedge areset) begin
        if(areset != 0)
            state = LEFT;
        else 
               state = next;
    end
    
    always @ (*) begin
        next = LEFT;
        
        case(state)
            LEFT: begin
                if(ground == 0)
                    next = FALL_L;
                else begin
                    if( bump_left != 0)
                        next = RIGHT;
                    else
                        next = LEFT;
                end
            end
            RIGHT: begin
                if(ground == 0)
                    next = FALL_R;
                else begin
                    if( bump_right != 0)
                        next = LEFT;
                    else
                        next = RIGHT;
                end
            end
            FALL_L: begin
                if(ground == 0)
                    next = FALL_L;
                else
                    next = LEFT;
            end
            FALL_R: begin
                if(ground == 0)
                    next = FALL_R;
                else
                    next = RIGHT;
            end
            default: next = LEFT;
        endcase
    end

    always @(*) begin
        case(state)
            LEFT: begin
                walk_left = 1;
                walk_right = 0;
                aaah = 0;
            end
            RIGHT: begin
                walk_left = 0;
                walk_right = 1;
                aaah = 0; 
            end
            FALL_L: begin
                walk_left = 0;
                walk_right = 0;
                aaah = 1; 
            end
            FALL_R: begin
                walk_left = 0;
                walk_right = 0;
                aaah = 1; 
            end
            default: begin
                walk_left = 1;
                walk_right = 0;
                aaah = 0;  
            end
        endcase
    end
    
endmodule