hdlbits.01xz.net /Circuits/Sequential Logic/Finite State Machines/Q6: FSM

module top_module (
    input clk,
    input reset,     // synchronous reset
    input w,
    output z);
    
    parameter A = 6'd1;
    parameter B = 6'd2;
    parameter C = 6'd3;
    parameter D = 6'd4;
    parameter E = 6'd5;
    parameter F = 6'd6;
    
    reg [5:0] state, next;
    
    //ff
    always@(posedge clk) begin
        if(reset)
            state = A;
        else
            state = next;
    end
    
    //trans
    always @(*) begin
        if(reset)
            next = A;
        else begin
            next = A;
            case(state)
                A:
                    next = w? A: B;
                B:
                    next = w? D: C;
                C:
                    next = w? D: E;
                D:
                    next = w? A: F;
                E:
                    next = w? D: E;
                F:
                    next = w? D: C;
                default
                    next = A;
            endcase
        end
    end
    //out
    assign z = ((state==E)||(state==F))?1'b1:1'b0;

endmodule