module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
reg [5:0] next;
assign next[0] = y[0]&(~w) | y[4]&(~w);
assign next[1] = y[0]&(w);
assign next[2] = y[1]&(w) | y[5]&(w);
assign next[3] = y[1]&(~w) | y[2]&(~w) | y[4]&(~w) | y[5]&(~w);
assign next[4] = y[2]&(w) | y[4]&(w);
assign next[5] = y[3]&(w);
assign Y1 = next[1];
assign Y3 = next[3];
endmodule
hdlbits.01xz.net /Circuits/Sequential Logic/Finite State Machines/Q2b: one-hot FSM equations
最新推荐文章于 2024-06-07 23:17:16 发布