hdlbits.01xz.net /Circuits/Building Larger Circuits/FSM: The complete FSM

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output shift_ena,
    output counting,
    input done_counting,
    output done,
    input ack );
    
    parameter S     = 10'd1;
    parameter S1     = 10'd2;
    parameter S11    = 10'd3;
    parameter S110     = 10'd4;
    parameter B0     = 10'd5;
    parameter B1     = 10'd6;
    parameter B2     = 10'd7;
    parameter B3     = 10'd8;
    parameter COUNT = 10'd9;
    parameter WAIT     = 10'd10;
    
    reg [9:0] state, next;
    
    reg d;
    
    assign d = data;
    
    //ff
    always @(posedge clk) begin
        if(reset)
            state = S;
        else
            state = next;
    end
    //trans
    always @(*) begin
        if(reset)
            next = S;
        else begin 
            case(state)
                S: begin
                    if(d==1)
                        next = S1;
                    else
                        next = S;
                end
                
                S1: begin
                    if(d==1)
                        next = S11;
                    else
                        next = S;
                end
                S11: begin
                    if(d==0)
                        next = S110;
                    else
                        next = S11;
                end
                S110: begin
                    if(d==1)
                        next = B0;
                    else
                        next = S;
                end
                B0: next = B1;
                B1: next = B2;
                B2: next = B3;
                B3: next = COUNT;
                COUNT: begin
                    if(done_counting)
                        next = WAIT;
                    else
                        next = COUNT;
                end
                WAIT: begin 
                    if(ack == 1)
                        next = S;
                    else
                        next = WAIT;
                end
            endcase
        end
    end
    //out
    assign shift_ena = ((state==B0)||(state==B1)||(state==B2)||(state==B3))? 1'b1: 1'b0;
    assign counting = (state==COUNT)? 1'b1: 1'b0;
    assign done = (state==WAIT)? 1'b1: 1'b0;

endmodule