PS2操作

1.整体框架

2.子模块
（1）PS2_Module

文件：PS2_Module.v
module PS2_Module(CLK,nRST,PS2_CLK_Pin_IN,PS2_Data_Pin_IN,PS2_Data,PS2_Done_Sig);
input CLK;
input nRST;
input PS2_CLK_Pin_IN;
input PS2_Data_Pin_IN;
output [7:0]PS2_Data;
output PS2_Done_Sig;

wire H2L_Sig;
Detect_Module U1
(
.CLK(CLK),.nRST(nRST),
.PS2_CLK_Pin_IN(PS2_CLK_Pin_IN),
.H2L_Sig(H2L_Sig)
);

PS2_Decoder_Module U2
(
.CLK(CLK),.nRST(nRST),
.H2L_Sig(H2L_Sig),
.PS2_Data_Pin_IN(PS2_Data_Pin_IN),
.PS2_Done_Sig(PS2_Done_Sig),
.PS2_Data(PS2_Data)
);
endmodule

文件：Detect_Module.v
module Detect_Module(CLK,nRST,PS2_CLK_Pin_IN,H2L_Sig);
input CLK;
input nRST;
input PS2_CLK_Pin_IN;
output H2L_Sig;

reg H2L_F1;
reg H2L_F2;
always @(posedge CLK or negedge nRST)
if(!nRST)
begin
H2L_F1<=1'b1;
H2L_F2<=1'b1;
end
else
begin
H2L_F1<=PS2_CLK_Pin_IN;
H2L_F2<=H2L_F1;
end

assign H2L_Sig=H2L_F2&!H2L_F1;

endmodule

文件： PS2_Decoder_Module.v
module PS2_Decoder_Module(CLK,nRST,H2L_Sig,PS2_Data_Pin_IN,PS2_Data,PS2_Done_Sig);
input CLK;
input nRST;
input H2L_Sig;
input PS2_Data_Pin_IN;
output [7:0]PS2_Data;
output PS2_Done_Sig;

reg [7:0]rData;
reg isDone;
reg [4:0]i;

always @(posedge CLK or negedge nRST)
if(!nRST)
begin
rData<=8'd0;
i<=5'd0;
isDone<=1'b0;
end
else
case(i)
5'd0:if(H2L_Sig) i<=i+1'b1;

   4'd1,4'd2,4'd3,4'd4, 
   4'd5,4'd6,4'd7,4'd8:if(H2L_Sig)
                        begin i<=i+1'b1;
                             rData[i-1]<=PS2_Data_Pin_IN;
                        end

   5'd9,5'd10:if(H2L_Sig) i<=i+1'b1;

   5'd11:if(rData==8'hf0)
             i<=5'd12;
          else
             i<=5'd23;

   5'd12,5'd13,5'd14,5'd15,5'd16,
   5'd17,5'd18,5'd19,5'd20,5'd21,5'd22:if(H2L_Sig)
                                         i<=i+1'b1;

   5'd23:begin i<=i+1'b1;
               isDone<=1'b1;
         end

   5'd24:begin
            i<=5'd0;
            isDone<=1'b0;
         end
 endcase

assign PS2_Done_Sig=isDone;
assign PS2_Data=rData;

endmodule

（2）Cmd_Control_Module

文件：Cmd_Control_Module.v
module Cmd_Control_Module(CLK,nRST,PS2_Data,Data_Out,PS2_Done_Sig);
input CLK;
input nRST;
input [7:0]PS2_Data;
input PS2_Done_Sig;
output [3:0]Data_Out;

reg [3:0]rData;
always @(posedge CLK or negedge nRST)
if(!nRST)
rData<=4'b0001;
else if(PS2_Done_Sig)
case(PS2_Data)
8'h1d: rData <= { rData[2:0], rData[3] }; 
8'h22: rData <= { rData[0], rData[3:1] }; 
8'h14: rData <= { rData[0],rData[1],rData[2],rData[3]};
endcase

assign Data_Out=rData;
endmodule