VITA 49.0协议阅读笔记

VITA 49.0标准定义了射频收发机和信号处理单元间的传输层协议,适用于频谱监测、通信和雷达等领域。协议提供了多种格式选项和高精度时间戳,以适应不同应用需求。本文详细介绍了IF数据包结构,包括Header、Timestamp、Packet Count、Stream ID等,并讨论了VRT Packet Stream、VRT Information Stream的概念及其关联规则。同时,阐述了数据包流和信息流的Class规范,以及时间戳的处理方式。此外,还涵盖了数据包Payload的结构和Context Packet的格式,强调了数据包与上下文包的配对规则及其在不同场景下的应用。
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Vita Radio Transport (VRT) standard 定义了一个在射频收发机和信号处理装置之间的具有广泛应用的一个的传输层协议 ,用于提升射频和信号处理单元之间的协同性,其应用包括频谱监测,通信,雷达等
VRT协议提供了大量的格式化的选项,去允许传输层对不同的应用进行优化。VRT还提供了一个高精度的时间戳去用来提供不同的接收通道的时间同步。
IF :Intermediate Frequency  中频 A frequency band, typically above the original base-band range of a signal, but below the intended transmit or receive band.
VRT Packet Stream : A VRT Packet Stream is a sequence of transmitted VRT compliant packets that are all used to convey the same information. A VRT Packet Stream may convey either IF Data, or IF Context, or Extension Data, or Extension Context.
VRT Information Stream :A VRT Information Stream is a collection of VRT Packet Streams, associated together according to VRT rules in order to transport a complete set of Data and Context for one or more related signals.
 
VRT Information Stream is a set of related VRT Packet Streams.
即VRT信息流是数据包流的合集。例如:其中的一个packet stream可能是数字化的采样数据,而与它在一块packet stream可能传递的是 RF 中心频点,带宽,功率,天线方向等。
 
 
Stream Identifiers 用来关联所有的packet Stream 到一起,成为information Stream。且Stream Identifiers是惟一的,同一packet stream 的stream ID是相同的
 
Class
VRT提出了控制 数据包流和信息流 结构和功能的规则
In the context of VRT the term Class means a specification of the structure and function of VRT objects
 
VRT Packet Class is the specification of the name, structure, and function of the packets in a VRT Packet Stream.
其功能规范描述了在每一个包内的每一个字段的解释意义,以及整个packet stream 的目的。
 
VRT Information Class is a specification of the structure and function of the Information Stream.
信息类别的作用 用来充当一个控制文件来创建 单一或者任意数量但功能相同的 information stream ,
下图为information class 和packet class 之间的关系。
class总共8个部件,
1. Class Name and Code  名字
2. Information Stream Purpose  意图, 例如表明数据包是干什么的,或者更具体的从哪里来到哪里去以及干什么。
3. Names of included VRT Packet Streams ,并不是说此处有packet stream,而是对系统设计者而言packet stream应该参考information stream
4. Purpose of each included Packet Stream ,表明
5. Packet Classes
6. Packet Stream Details
7. Reference Points,context在系统中应用的地点,可以是射频的也可以是数字的,可以是VRT数据流中也可以是非VRT协议的数据流,详见 附录B
8. Packet Stream Associations  , 数据包的之间的匹配,共有5种类型,其中包括
                8.1 Data-Context pairing  在匹配的packet stream 中公用 stream Identifiers 
                8.2 Source Context association, 用来清除哪个context是从上游来的并且到下游哪个地方去,
                8.3 Vector-component Context association  ,用于data packet stream 包含矢量数据,多个数据用于一处
                8.4 Asynchronous-channel Context association,单一的 data packet  stream 可能用于多个异步数据通道,
                8.5 System Context association
 
 
下图为例子用来阐述 packet stream association
 
 
Packet Stream Associations
关联关系总共有5种,
。data - context pairing 
。source context association 
。vector - component context association
。asynchronous - channel context association 
。system context association 
 
图中的 双箭头的pair 表明的是 data 和 context 的匹配,其他 context packet 与 data都是间接的联系,通过context packet 之间的联系建立起来的链来协同作用, 且配对 是独一无二的
 
Reference-Point Time of an event is the time that the information (in the signal) corresponding to the event was present at the Reference Point
参考点时间用来表示信息在参考点发生的时间。
VRT 可以支持多个时间参考点以及其他类型的context。
 
 
IF Data Packet 
下图为Data packet 的模板
 
optional 字段如果没有的话直接去掉就行,不用补零
其中 Header 部分如下
 
  :   indicates whether the Class Identifier (Class ID) field is included in a packet ,有无 class ID 
T    :   indicates whether the trailer is included in a packet  , 有无尾部。
R    :   reserved for future use in VRT ,保留字段。
TSI :    (TimeStamp-Integer) indicating which, if any, type of Integer-seconds Timestamp is present in the packet. 如果有时间戳的话指示时间戳的整数部分是啥类型的,
TSF : (TimeStamp-Fractional)indicating which, if any, type of Fractional-seconds Timestamp is present in the packet 指示时间戳小数部分来源
Packet Count :  Packet Count shall increment in each consecutive IF Data packet having the same Stream Identifier and the same packe
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Abstract This standard describes VITA 46.0 Advanced Module Format for VMEbus systems, an evolutionary step forward for the provision of high-speed interconnects in harsh-environment applications. Foreword VME has been the de-facto bus standard for Commercial off the Shelf ( COTS ) Circuit Card Assemblies since the 1980’s. VME boards have proven to be remarkably capable of evolving to support newer technologies with innovations such as VME Subsystem Bus, PCI Mezzanine Cards (PMC’s) and VME320. However, advances in technologies, appearing particularly in interconnects, have demonstrated the need for an advance in system development. This advance needs to accommodate high speed interconnect, particularly serial interconnects, and higher power delivery in concert with better heat removal. This draft standard addresses these needs in the context of IEEE 1101 form factor modules. Other specifications may address alternate outlines, such as VITA-48 (Draft). Because electronics miniaturization is driving the plug-in module I/O count, most system interconnects will need:  Multi-gigabit differential technology  Core computing cluster switched fabrics  Serial RapidIO, PCI Express, Advanced Switching Interconnect  Sufficient ports to enable distributed switching or centralized switching The plethora of high-speed interfaces available for tomorrow’s plug-in modules:  Network interfaces (Fibre Channel, 10 GbE XAUI, Infiniband…,)  Digital video (TMDS, PanelLink, OpenLDI…)  Mass storage interface (Fibre Channel, Serial ATA…,)  FPGA-based inter-board connections (e.g. Xilinx RocketIO)  Custom sensor interfaces VITA 46 provides an evolutionary roadmap for VME users:  To leverage the broad spectrum of high-speed interconnect technologies  Backward compatibility with VME bus electrical, software and selected mechanicals  Enables heterogeneous architectures which preserve existing investments in COTS-based systems  Addresses both 3U and 6U form factors with commonality  Harsh environment fit ‘designed-in’ up front in the standard  Rugged air or conduction-cooled form factors  High value placed on rear-panel I/O  High-speed connector survivability/compliance
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