Parsing PCB Editor netlist files 

最新推荐文章于 2022-11-14 10:42:42 发布
最新推荐文章于 2022-11-14 10:42:42 发布
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分类专栏： EDA netlist
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本文链接：https://blog.csdn.net/wang161019/article/details/112271097
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该博客详细介绍了如何解析PCB编辑器的三种网列表文件：PSTCHIP.DAT包含物理部件描述，PSTXNET.DAT是连接性文件，列出每个网络及其属性，而PSTXPRT.DAT则列出了每个参考设计ator和分配给它的部分。
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目录

Parsing PCB Editor netlist files 

PSTCHIP.DAT

PSTCHIP File format

PSTCHIP File Elements

PSTCHIP Sample file

PSTCHIP.DAT

PSTXNET File Elements

PSTXNET File format

PSTXNET Sample file

PSTXPRT.DAT

PSTXPRT File Elements

PSTXPRT File format

PSTXPRT Sample file

Parsing PCB Editor netlist files 

PSTCHIP.DAT

  • The PSTCHIP.DAT file contains a description for each physical part used in a Capture design. The Capture netlister extracts this physical description from properties on all occurrences rather than just instances.

PSTCHIP File format

  • Here is the file format for the PSTCHIP.DAT file:

FILE_TYPE=LIBRARY_PARTS;
primitive 'Part Name';
pin
'Name':
PIN_NUMBER='(Number,Number...)';
INPUT_LOAD='(*)';
OUTPUT_LOAD='(*)';
OUTPUT_TYPE='(Type)';
PIN_GROUP='PinGroup';
.
.
.
end_pin;
body
POWER_PINS='(Power:Number;Ground:Number)';
PART_NAME='Source Package';
JEDEC_TYPE='PCB Footprint';
VALUE='Value';
NC_PINS='(Number,Number)';
Package (Component Definition) Property='occurrence_value;
.
.
.
end_body;
end_primitive;
END.

PSTCHIP File Elements

PSTCHIP.DAT section

Description

Header

This line begins the PSTCHIP.DAT file by declaring the file type. A PSTCHIP.DAT file always starts with the FILE_TYPE=LIBRARY_PARTS statement.

primitive

A primitive is the description of the physical part.

Part Name

Concatenation of Source Package, PCB Footprint and other properties found in the [ComponentDefinitionProps] section of the configuration file used for netlisting.

pin

Starts the pin section.

Name

Pin name. There is a section for every pin name.

Number, Number...

The pin number for that pin name. If you have a multi-section part, then the pin numbers containing that pin name are separated by commas.

INPUT_LOAD

The netlister assigns this property to an input pin. The input local current is measured in milliamperes. If there is an output load on an output pin you get an OUTPUT_LOAD property.

OUTPUT_TYPE

Netlister assigns this property to define an output pin as open collector, open-emitter, or tri-state (3 state). This data is used to make sure all outputs on a net have the same output type. The OUTPUT_TYPE property also specifies the logic function created by tying the outputs together.

Type

Value of the output pin type when open collector, open emitter, 3 state.

PinGroup

This is taken from the PinGroup column in the part editor package property spreadsheet. To see the spreadsheet, from the Package menu choose View, then from the Properties menu choose Edit. This property only shows up in PSTCHIP.DAT if you have a positive value for PinGroup meaning that pin is swappable with the other input pins for that section in the multi-section part.

Power:Numbers; Ground:Numbers

This POWER_PINS line defines the default power and ground requirements for the physical part. Power or ground pins that need to be connected together on the board will share the same name. This syntax for this line is:

name of your power pins (VCC for example):the numbers of the power pins; the name of the ground pins:the numbers of the ground pins

NC_PINS

Describes the pins not connected to the logic, but which are present in the physical package. Currently the netlister gets this value from an NC property added to the part and this property has a value of the pins you want to be no connects; these values are separated by commas. You can also cause this line to be generated if you put a no-connect symbol on a pin in the schematic. This property doesn’t show up if you don’t have any NC pins in your design.

Package (Component Definition) Property

Any property found in the property editor on a part that is specified as a property to use in the [ComponentDefinitionProps] section of the configuration file. Properties are separated by commas. The last property is followed by a semicolon. There can by any number of properties. PART_NAME, JEDEC_TYPE, and VALUE are always given in this section regardless of what is in the configuration file.

occurrence_value

The occurrence value of the property is given between the single quotation marks.

PSTCHIP Sample file

  • The PSTCHIP.DAT file contains one or more primitives, organized into a pin section and a body section. Here is an example:
FILE_TYPE=LIBRARY_PARTS;
{ Using PSTWRITER 14.0-p002 Oct-09-2000 at 10:32:05}
primitive 'OR14';
pin
'I0':
PIN_NUMBER='(1,4,9,12)';
INPUT_LOAD='(*)';
PIN_GROUP='1';
'I1':
PIN_NUMBER='(2,5,10,13)';
INPUT_LOAD='(*)';
PIN_GROUP='1';
'O':
PIN_NUMBER='(3,6,8,11)';
OUTPUT_LOAD='(*)';
end_pin;
body
POWER_PINS='(VCC:14)';
POWER_PINS='(GND:7)';
PART_NAME='74LS32_0';
CLASS='IC';
JEDEC_TYPE='dip14_3';
VALUE='74LS32';
end_body;
end_primitive;
primitive 'AND14';
pin
'I0':
PIN_NUMBER='(1,4,9,12)';
INPUT_LOAD='(*)';
PIN_GROUP='1';
'I1':
PIN_NUMBER='(2,5,10,13)';
INPUT_LOAD='(*)';
PIN_GROUP='1';
'O':
PIN_NUMBER='(3,6,8,11)';
OUTPUT_LOAD='(*)';
end_pin;
body
POWER_PINS='(VCC:14)';
POWER_PINS='(GND:7)';
PART_NAME='74LS08_0';
CLASS='IC';
JEDEC_TYPE='dip14_3';
VALUE='74LS08';
end_body;
end_primitive;
primitive '74LS04_IC_DIP14_3_74LS04';
pin
'I':
PIN_NUMBER='(1,3,5,9,11,13)';
INPUT_LOAD='(*)';
'O':
PIN_NUMBER='(2,4,6,8,10,12)';
OUTPUT_LOAD='(*)';
end_pin;
body
POWER_PINS='(VCC:14)';
POWER_PINS='(GND:7)';
PART_NAME='74LS04';
CLASS='IC';
JEDEC_TYPE='dip14_3';
VALUE='74LS04';
end_body;
end_primitive;
END.

PSTCHIP.DAT

  • The PSTXNET.DAT file is the connectivity file. This file lists each net, its properties, its attached nodes, and node properties. The list is ordered by physical net name and contains all net properties and the logic-to-physical binding of nets and nodes.

PSTXNET File Elements

PSTXNET.DAT section

Description

NET_NAME

Marks the beginning of a net entry. The net name entry always ends with a semicolon after the net property list.

'Name'

Name of the net or the value of the Name property. If you have a net alias, it is used as the name. This is the flat net name, so if a child schematic has a different name or alias than the same net on the root, the name or alias on the root is the one that gets used.

Canonical Path

The first canonical path uniquely identifies each net in your schematics. It contains your design name, schematic folders, name, and other identifiers.

NODE_NAME

Marks the beginning of a node entry. The node name entry always ends with a semicolon after the node property list.

Reference

The reference of the physical part.

Number

The pin number on the part attached to the net.

Canonical Path

The second canonical path uniquely identifies each part the net is attached to in your schematic pages. It contains your design name, schematic folders, ID, and other identifiers.

Type

Pin type of the pin attached to the net: input (I), output (O), bidirectional (IO), and so on.

Net Property

Any property found in the property editor that is specified as a property to use in the configuration file, [netprops] section. Properties are separated by commas. The last property in the list is followed by a semicolon. There can by any number of properties. An example would be ECL='TRUE';

occurrence_value

The occurrence value of the property is given between the single quotation marks.

PSTXNET File format

FILE_TYPE=EXPANDEDNETLIST;
NET_NAME
'Name'
'Canonical Path';
NODE_NAME Reference Number
'Canonical Path':
'Type':;
Net Property='occurrence_value',
.
.
. ;
END.

PSTXNET Sample file

FILE_TYPE = EXPANDEDNETLIST;
{ Using PSTWRITER 14.0-p002 Oct-09-2000 at 10:32:05 }
NET_NAME
'N00011'
'@FULLADD.FULLADD(SCH_1):N00011':
C_SIGNAL='@fulladd.fulladd(sch_1):n00011',
ECL='TRUE';
NODE_NAME U3 3
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679612@TTL.74LS04.NORMAL(CHIPS)':
'I':;
NODE_NAME U2 4
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679613@FULLADD.74LS08_0.NORMAL(CHIPS)':
'I0':;
NODE_NAME U2 9
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679614@FULLADD.74LS08_0.NORMAL(CHIPS)':
'I0':;
NODE_NAME U1 8
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679615@FULLADD.74LS32_0.NORMAL(CHIPS)':
'O':;
NET_NAME
'SUM'
'@FULLADD.FULLADD(SCH_1):SUM':
C_SIGNAL='@fulladd.fulladd(sch_1):sum';
NODE_NAME U1 6
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679615@FULLADD.74LS32_0.NORMAL(CHIPS)':
 'O':;
NET_NAME
'X'
'@FULLADD.FULLADD(SCH_1):X':
C_SIGNAL='@fulladd.fulladd(sch_1):x';
NODE_NAME U3 5
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679610@TTL.74LS04.NORMAL(CHIPS)':
'I':;
NODE_NAME U2 12
 '@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679611@FULLADD.74LS08_0.NORMAL(CHIPS)':
'I0':;
NODE_NAME U4 5
 '@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679614@FULLADD.74LS08_0.NORMAL(CHIPS)':
'I1':;
NET_NAME
'Y'
'@FULLADD.FULLADD(SCH_1):Y':
C_SIGNAL='@fulladd.fulladd(sch_1):y';
NODE_NAME U3 9
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679612@TTL.74LS04.NORMAL(CHIPS)':
'I':;
NODE_NAME U4 1
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679613@FULLADD.74LS08_0.NORMAL(CHIPS)':
'I0':;
NODE_NAME U4 4
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679614@FULLADD.74LS08_0.NORMAL(CHIPS)':
'I0':;
NET_NAME
'CARRY_IN'
'@FULLADD.FULLADD(SCH_1):CARRY_IN':
C_SIGNAL='@fulladd.fulladd(sch_1):carry_in';
NODE_NAME U3 1
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679610@TTL.74LS04.NORMAL(CHIPS)':
'I':;
NODE_NAME U2 1
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679611@FULLADD.74LS08_0.NORMAL(CHIPS)':
'I0':;
NODE_NAME U2 10
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679614@FULLADD.74LS08_0.NORMAL(CHIPS)':
'I1':;
NET_NAME
'N00013'
'@FULLADD.FULLADD(SCH_1):N00013':
C_SIGNAL='@fulladd.fulladd(sch_1):n00013';
NODE_NAME U1 1
'@FULLADD.FULLADD(SCH_1):I505679590@FULLADD.74LS32_0.NORMAL(CHIPS)':
'I0':;
NODE_NAME U2 8
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679614@FULLADD.74LS08_0.NORMAL(CHIPS)':
'O':;
NET_NAME
'N00023'
'@FULLADD.FULLADD(SCH_1):N00023':
C_SIGNAL='@fulladd.fulladd(sch_1):n00023';
NODE_NAME	U1 2
'@FULLADD.FULLADD(SCH_1):I505679590@FULLADD.74LS32_0.NORMAL(CHIPS)':
'I1':;
NODE_NAME U4 6
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679614@FULLADD.74LS08_0.NORMAL(CHIPS)':
'O':;
NET_NAME
'CARRY_OUT'
'@FULLADD.FULLADD(SCH_1):CARRY_OUT':
C_SIGNAL='@fulladd.fulladd(sch_1):carry_out';
NODE_NAME	U1 3
'@FULLADD.FULLADD(SCH_1):I505679590@FULLADD.74LS32_0.NORMAL(CHIPS)':
'O':;
NET_NAME
'X_BAR'
'@FULLADD.FULLADD(SCH_1):X_BAR':
C_SIGNAL='@fulladd.fulladd(sch_1):x_bar';
NODE_NAME U3 2
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679610@TTL.74LS04.NORMAL(CHIPS)':
'O':;
NODE_NAME U2 5
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679613@FULLADD.74LS08_0.NORMAL(CHIPS)':
'I1':;
NET_NAME
'N5056796111'
'@FULLADD.FULLADD(SCH_1):N5056796111':
C_SIGNAL='@fulladd.fulladd(sch_1):n5056796111';
NODE_NAME U2 2
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679611@FULLADD.74LS08_0.NORMAL(CHIPS)':
'I1':;
NODE_NAME U3 4
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679612@TTL.74LS04.NORMAL(CHIPS)':
'O':;
NET_NAME
'N00032'
'@FULLADD.FULLADD(SCH_1):N00032':
C_SIGNAL='@fulladd.fulladd(sch_1):n00032';
NODE_NAME U2 3
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679611@FULLADD.74LS08_0.NORMAL(CHIPS)':
'O':;
NODE_NAME U1 4
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679615@FULLADD.74LS32_0.NORMAL(CHIPS)':
'I0':;
NET_NAME
'N00034'
'@FULLADD.FULLADD(SCH_1):N00034':
C_SIGNAL='@fulladd.fulladd(sch_1):n00034';
NODE_NAME U1 5
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679615@FULLADD.74LS32_0.NORMAL(CHIPS)':
'I1':;
NODE_NAME U2 6
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679613@FULLADD.74LS08_0.NORMAL(CHIPS)':
'O':;
NET_NAME
'X_BAR_74'
'@FULLADD.FULLADD(SCH_1):X_BAR_74':
C_SIGNAL='@fulladd.fulladd(sch_1):x_bar_74';
NODE_NAME U3 6
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679610@TTL.74LS04.NORMAL(CHIPS)':
'O':;
NODE_NAME U4 2
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679613@FULLADD.74LS08_0.NORMAL(CHIPS)':
 'I1':;
NET_NAME
'N5056796111_76'
'@FULLADD.FULLADD(SCH_1):N5056796111_76':
C_SIGNAL='@fulladd.fulladd(sch_1):n5056796111_76';
NODE_NAME U2 13
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679611@FULLADD.74LS08_0.NORMAL(CHIPS)':
'I1':;
NODE_NAME U3 8
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679612@TTL.74LS04.NORMAL(CHIPS)':
'O':;
NET_NAME
'N00032_77'
'@FULLADD.FULLADD(SCH_1):N00032_77':
C_SIGNAL='@fulladd.fulladd(sch_1):n00032_77';
NODE_NAME U2 11
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679611@FULLADD.74LS08_0.NORMAL(CHIPS)':
'O':;
NODE_NAME U1 9
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679615@FULLADD.74LS32_0.NORMAL(CHIPS)':
'I0':;
NET_NAME
'N00034_79'
'@FULLADD.FULLADD(SCH_1):N00034_79':
C_SIGNAL='@fulladd.fulladd(sch_1):n00034_79';
NODE_NAME U1 10
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679615@FULLADD.74LS32_0.NORMAL(CHIPS)':
'I1':;
NODE_NAME U4 3
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679613@FULLADD.74LS08_0.NORMAL(CHIPS)':
'O':;
END.

PSTXPRT.DAT

  • The PSTXPRT.DAT file (the expanded part list) lists each reference designator and the sections assigned to it. The PSTXPRT.DAT file is ordered by reference designator and section number.

PSTXPRT File Elements

PSTXPRT.DAT section

Description

DIRECTIVES

Marks the beginning of the directives section. Directives always end with a semicolon.

PST_VERSION

Version of PCB Editor interface.

ROOT_DRAWING

Root schematic folder of design in Capture.

POST_TIME

Date and time of netlist.

SOURCE_TOOL

Tool used is Capture Writer or Design Entry HDL Writer.

END_DIRECTIVES

Marks the end of the Directives section.

Part Reference

The reference designator name of the physical part.

ComponentInstanceProperty

Properties and values of any component instance (package) properties found on the part and listed in the configuration file under the [ComponentInstanceProperty] section.

PART NAME

Concatenation of Source Package, PCB Footprint, and other properties found in the [ComponentDefinitionProps] section of the configuration file used for netlisting.

SECTION_NUMBER #

Marks the beginning of a physical section number. Each section of the package used gets its own section number. Single section parts have only one section number.

Canonical path

The canonical path uniquely identifies each part in your schematic pages. It contains your design name, schematic folders, part ID, source part, implementation type, and other identifiers.

Physical path

The physical path uniquely identifies each part in a design. The physical path contains the design name, schematic folder, page number, part ID, source part, implementation type, and other identifiers specific to the selected part in the design.

Part (function) property

Any property found in the property editor that is specified as a property to use in the configuration file, [functionprops] section. Properties are separated by commas. The last property in the list is followed by a semicolon. There can by any number of properties.

occurrence_value

The occurrence value of the property is given between the single quotation marks.

PRIM_FILE

Location of the where package properties are listed. This is the PSTCHIP.DAT file which is closely linked to the PSTXPRT.DAT file.

designator

The designator is now stored so that we know if designators are numeric or alphabetic.

PSTXPRT File format

FILE_TYPE = EXPANDEDPARTLIST;
DIRECTIVES
PST_VERSION='PST_HDL_CENTRIC_VERSION_0';
ROOT_DRAWING = 'Root schematic folder of design' ;
POST_TIME = 'Date and Time of Netlist' ;
SOURCE_TOOL='Capture_Writer';
END_DIRECTIVES ;
PART_NAME
Part Reference ’PART NAME’;
ComponentInstanceProperty='occurence_value';
.
.
SECTION_NUMBER #
'Canonical path',
'Physical path',
Part(function) property='occurrence_value',
.
.
.
PRIM_FILE='.\pstchip.dat',
SECTION='designator';
END.

PSTXPRT Sample file

FILE_TYPE = EXPANDEDPARTLIST;
{ Using PSTWRITER 16.5.0 p001Apr-05-2011 at 10:09:06 }
DIRECTIVES
 PST_VERSION='PST_HDL_CENTRIC_VERSION_0';
 ROOT_DRAWING='FULLADD';
 POST_TIME='Mar 29 2011 00:05:38';
 SOURCE_TOOL='CAPTURE_WRITER';
END_DIRECTIVES;

PART_NAME
 U1 'ORGATE':;

SECTION_NUMBER 1
 '@FULLADD.FULLADD(SCH_1):I505679590@FULLADD.74LS32.NORMAL(CHIPS)':
 C_PATH='@fulladd.fulladd(sch_1):i505679590@fulladd.\74ls32.normal\(chips)',
 P_PATH='@fulladd.fulladd(sch_1):page1_i505679590@fulladd.\74ls32.normal\(chips)',
 PRIM_FILE='.\pstchip.dat',
 SECTION='A';

SECTION_NUMBER 2
 '@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679615@FULLADD.74LS32.NORMAL(CHIPS)':
 C_PATH='@fulladd.fulladd(sch_1):halfadd_a@fulladd.halfadd(sch_1):i505679615@fulladd.\74ls32.normal\(chips)',
 P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_a@fulladd.halfadd(sch_1):page2_i505679615@fulladd.\74ls32.normal\(chips)',
 PRIM_FILE='.\pstchip.dat',
 SECTION='B';

SECTION_NUMBER 3
 '@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679615@FULLADD.74LS32.NORMAL(CHIPS)':
 C_PATH='@fulladd.fulladd(sch_1):halfadd_b@fulladd.halfadd(sch_1):i505679615@fulladd.\74ls32.normal\(chips)',
 P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_b@fulladd.halfadd(sch_1):page2_i505679615@fulladd.\74ls32.normal\(chips)',
 PRIM_FILE='.\pstchip.dat',
 SECTION='C';

PART_NAME
 U2 'ANDGATE':;

SECTION_NUMBER 1
 '@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679611@FULLADD.74LS08.NORMAL(CHIPS)':
 C_PATH='@fulladd.fulladd(sch_1):halfadd_a@fulladd.halfadd(sch_1):i505679611@fulladd.\74ls08.normal\(chips)',
 P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_a@fulladd.halfadd(sch_1):page2_i505679611@fulladd.\74ls08.normal\(chips)',
 PRIM_FILE='.\pstchip.dat',
 SECTION='A';

SECTION_NUMBER 2
 '@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679613@FULLADD.74LS08.NORMAL(CHIPS)':
 C_PATH='@fulladd.fulladd(sch_1):halfadd_a@fulladd.halfadd(sch_1):i505679613@fulladd.\74ls08.normal\(chips)',
 P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_a@fulladd.halfadd(sch_1):page2_i505679613@fulladd.\74ls08.normal\(chips)',
 PRIM_FILE='.\pstchip.dat',
 SECTION='B';

SECTION_NUMBER 3
 '@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679614@FULLADD.74LS08.NORMAL(CHIPS)':
 C_PATH='@fulladd.fulladd(sch_1):halfadd_a@fulladd.halfadd(sch_1):i505679614@fulladd.\74ls08.normal\(chips)',
 P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_a@fulladd.halfadd(sch_1):page2_i505679614@fulladd.\74ls08.normal\(chips)',
 PRIM_FILE='.\pstchip.dat',
 SECTION='C';

SECTION_NUMBER 4
 '@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679611@FULLADD.74LS08.NORMAL(CHIPS)':
 C_PATH='@fulladd.fulladd(sch_1):halfadd_b@fulladd.halfadd(sch_1):i505679611@fulladd.\74ls08.normal\(chips)',
 P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_b@fulladd.halfadd(sch_1):page2_i505679611@fulladd.\74ls08.normal\(chips)',
 PRIM_FILE='.\pstchip.dat',
 SECTION='D';

PART_NAME
 U3 'NOTGATE':;

SECTION_NUMBER 1
 '@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679610@FULLADD.74LS04.NORMAL(CHIPS)':
 C_PATH='@fulladd.fulladd(sch_1):halfadd_a@fulladd.halfadd(sch_1):i505679610@fulladd.\74ls04.normal\(chips)',
 P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_a@fulladd.halfadd(sch_1):page2_i505679610@fulladd.\74ls04.normal\(chips)',
 PRIM_FILE='.\pstchip.dat',
 SECTION='A';

SECTION_NUMBER 2
 '@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679612@FULLADD.74LS04.NORMAL(CHIPS)':
 C_PATH='@fulladd.fulladd(sch_1):halfadd_a@fulladd.halfadd(sch_1):i505679612@fulladd.\74ls04.normal\(chips)',
 P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_a@fulladd.halfadd(sch_1):page2_i505679612@fulladd.\74ls04.normal\(chips)',
 PRIM_FILE='.\pstchip.dat',
 SECTION='B';

SECTION_NUMBER 3
 '@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679610@FULLADD.74LS04.NORMAL(CHIPS)':
 C_PATH='@fulladd.fulladd(sch_1):halfadd_b@fulladd.halfadd(sch_1):i505679610@fulladd.\74ls04.normal\(chips)',
 P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_b@fulladd.halfadd(sch_1):page2_i505679610@fulladd.\74ls04.normal\(chips)',
 PRIM_FILE='.\pstchip.dat',
 SECTION='C';

SECTION_NUMBER 4
 '@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679612@FULLADD.74LS04.NORMAL(CHIPS)':
 C_PATH='@fulladd.fulladd(sch_1):halfadd_b@fulladd.halfadd(sch_1):i505679612@fulladd.\74ls04.normal\(chips)',
 P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_b@fulladd.halfadd(sch_1):page2_i505679612@fulladd.\74ls04.normal\(chips)',
 PRIM_FILE='.\pstchip.dat',
 SECTION='D';

PART_NAME
 U4 'ANDGATE':;

SECTION_NUMBER 1
 '@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679613@FULLADD.74LS08.NORMAL(CHIPS)':
 C_PATH='@fulladd.fulladd(sch_1):halfadd_b@fulladd.halfadd(sch_1):i505679613@fulladd.\74ls08.normal\(chips)',
 P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_b@fulladd.halfadd(sch_1):page2_i505679613@fulladd.\74ls08.normal\(chips)',
 PRIM_FILE='.\pstchip.dat',
 SECTION='A';

SECTION_NUMBER 2
 '@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679614@FULLADD.74LS08.NORMAL(CHIPS)':
 C_PATH='@fulladd.fulladd(sch_1):halfadd_b@fulladd.halfadd(sch_1):i505679614@fulladd.\74ls08.normal\(chips)',
 P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_b@fulladd.halfadd(sch_1):page2_i505679614@fulladd.\74ls08.normal\(chips)',
 PRIM_FILE='.\pstchip.dat',
 SECTION='B';

END.

 

Finn Wang
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