Cadence网表文件解析

最新推荐文章于 2023-07-23 08:20:08 发布
最新推荐文章于 2023-07-23 08:20:08 发布
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分类专栏： HW 文章标签： 网表 Cadence OrCAD

Cadence网表文件解析

概述

Cadence网表文件由：PSTCHIP.DAT ，PSTXPRT.DAT和PSTXNET.DAT组成。

文件名描述备注
PSTCHIP.DAT该文件包含了设计中用到的每个类型组件的描述
PSTXPRT.DAT该文件也被称为扩展元件列表，包含了物理元件列表，罗列了每个位号以及所述的区域，按照位号和区域排序
PSTXNET.DAT该文件是互联文件，也被称之为扩展网络列表，包含了设计中的每个网络以及跟它关联的属性，节点和节点属性，列表按照物理网络名称排序

注释

All pins that are not connected to a net (whether with a No Connect symbol, or otherwise) appear in the PSTXNET.DAT file, as nets with the name “NC.” Therefore, you should avoid the net alias “NC” in your design. The NC property discussed in the first option, above, appears in the PSTCHIP.DAT file in the NC_PINS line rather than being added to the NC net in PSTXNET.DAT/PSTXPRT.DAT. Therefore, all pins connected to the NC net are unconnected on the PC board.

How properties are netlisted from Capture to PCB Editor

Not all properties in the configuration file show up as properties in PCB Editor. Some of these
properties are used in generating portions of the netlist PST*.DAT files.
In PCB Editor, component properties (package properties in Capture) take precedence over
function properties (part properties in Capture). So in the netlist, a package property value is used if
both a part and package have values for the same property. Capture always uses the occurrence
values in the netlist.
Package (component) properties, which are found in the PSTCHIP.DAT and PSTXPRT.DAT netlist
files, can be viewed in PCB Editor using the Show Element command on a component. For
example, PCB Editor has defined VALUE as a Component Definition property so it appears under
this heading in the Show Element dialog box. Other properties such as CLASS or JEDEC_TYPE
are also listed.
Part (function) properties are found in the PSTXNET.DAT file and can appear as Component
Definition properties if they are predefined in PCB Editor and if you list them in the
[ComponentDefinitionProps] section of the configuration file. Function properties are listed in the
[functionprops] section of the configuration file.
Net properties appear in the PSTXNET.DAT/PSTXPRT.DAT file under the NET_NAME section.
For a design, you can have multiple configuration files. However, the configuration file to be used
while generating PCB Editor netlist needs to be specified in the Setup dialog box launched from the
PCB Editor tab of the Create Netlist dialog box.

PCB编辑器Netlist文件

PSTCHIP.DAT

该文件包含了Capture设计中所用每个物理元件的描述信息。Capture

PSTCHIP文件格式

FILE_TYPE=LIBRARY_PARTS;
primitive 'Part Name';
pin
'Name':
PIN_NUMBER='(Number,Number...)';
INPUT_LOAD='(*)';
OUTPUT_LOAD='(*)';
OUTPUT_TYPE='(Type)';
PIN_GROUP='PinGroup';
.
.
.
end_pin;
body
POWER_PINS='(Power:Number;Ground:Number)';
PART_NAME='Source Package';
JEDEC_TYPE='PCB Footprint';
VALUE='Value';
NC_PINS='(Number,Number)';
Package (Component Definition) Property='occurrence_value;
.
.
.
end_body;
end_primitive;
END.

PSTCHIP文件元素

PSTCHIP.DAT Section描述备注
HeaderThis line begins the PSTCHIP.DAT file by declaring the file type. A PSTCHIP.DAT file always starts with the FILE_TYPE=LIBRARY_PARTS statement.
PrimitiveA primitive is the description of the physical part.
Part NameConcatenation of Source Package, PCB Footprint and other properties found in the [ComponentDefinitionProps] section of the configuration file used for netlisting.
PinStarts the pin section
NamePin name. There is a section for every pin name.
Number,Number…The pin number for that pin name. if you have a multi-section part, then the pin numbers contaning that pin name are separated by commas
INPUT_LOADThe netlister assigns this property to an input pin. The input local current is measured in milliamperes. If there is an output load on an output pin you get an OUTPUT_LOAD property.
OUTPUT_TYPENetlister assigns this property to define an output pin as open collector, open-emitter, or tri-state (3 state). This data is used to make sure all outputs on a net have the same output type. The OUTPUT_TYPE property also specifies the logic function created by tying the outputs together.
TypeValue of the output pin type when open collector, open emitter, 3 state
PinGroupThis is taken from the PinGroup column in the part editor package property spreadsheet. To see the spreadsheet, from the Package menu choose View, then from the Properties menu choose Edit. This property only shows up in PSTCHIP.DAT if you have a positive value for PinGroup meaning that pin is swappable with the other input pins for that section in the multi-section part
Power：Number; Ground:NumbersThis POWER_PINS line defines the default power and ground requirements for the physical part. Power or ground pins that need to be connected together on the board will share the same name. This syntax for this line is: name of your power pins (VCC for example):the numbers of the power pins; the name of the ground pins:the numbers of the ground pins
NC_PINSDescribes the pins not connected to the logic, but which are present in the physical package. Currently the netlister gets this value from an NC property added to the part and this property has a value of the pins you want to be no connects; these values are separated by commas. You can also cause this line to be generated if you put a no-connect symbol on a pin in the schematic. This property doesn’t show up if you don’t have any NC pins in your design.
Package(Component Definition Property)Any property found in the property editor on a part that is specified as a property to use in the [ComponentDefinitionProps] section of the configuration file. Properties are separated by commas. The last property is followed by a semicolon. There can by any number of properties.PART_NAME, JEDEC_TYPE, and VALUE are always given in this section regardless of what is in the configuration file.
occurrence_valueThe occurrence value of the property is given between the single quotation marks.

PSTCHIP样例

The PSTCHIP.DAT file contains one or more primitives, organized into a pin section and a body section.

FILE_TYPE=LIBRARY_PARTS;
{ Using PSTWRITER 14.0-p002 Oct-09-2000 at 10:32:05}
primitive 'OR14';
pin
'I0':
PIN_NUMBER='(1,4,9,12)';
INPUT_LOAD='(*)';
PIN_GROUP='1';
'I1':
PIN_NUMBER='(2,5,10,13)';
INPUT_LOAD='(*)';
PIN_GROUP='1';
'O':
PIN_NUMBER='(3,6,8,11)';
OUTPUT_LOAD='(*)';
end_pin;
body
POWER_PINS='(VCC:14)';
POWER_PINS='(GND:7)';
PART_NAME='74LS32_0';
CLASS='IC';
JEDEC_TYPE='dip14_3';
VALUE='74LS32';
end_body;
end_primitive;
primitive 'AND14';
pin
'I0':
PIN_NUMBER='(1,4,9,12)';
INPUT_LOAD='(*)';
PIN_GROUP='1'; 
'I1':
PIN_NUMBER='(2,5,10,13)';
INPUT_LOAD='(*)';
PIN_GROUP='1';
'O':
PIN_NUMBER='(3,6,8,11)';
OUTPUT_LOAD='(*)';
end_pin;
body
POWER_PINS='(VCC:14)';
POWER_PINS='(GND:7)';
PART_NAME='74LS08_0';
CLASS='IC';
JEDEC_TYPE='dip14_3';
VALUE='74LS08';
end_body;
end_primitive;
primitive '74LS04_IC_DIP14_3_74LS04';
pin
'I':
PIN_NUMBER='(1,3,5,9,11,13)';
INPUT_LOAD='(*)';
'O':
PIN_NUMBER='(2,4,6,8,10,12)';
OUTPUT_LOAD='(*)';
end_pin;
body
POWER_PINS='(VCC:14)';
POWER_PINS='(GND:7)';
PART_NAME='74LS04';
CLASS='IC';
JEDEC_TYPE='dip14_3';
VALUE='74LS04';
end_body;
end_primitive;
END.

PSTXNET.DAT

PSTXNET.DAT的组成元素

​ PSTXNET.DAT sectionDescription
NET_NAMEMarks the beginning of a net entry. The net name entry always ends with a semicolon after the net property list.
‘Name’Name of the net or the value of the Name property. If you have a net alias, it is used as the name. This is the flat net name, so if a child schematic has a different name or alias than the same net on the root, the name or alias on the root is the one that gets used.
Canonical PathThe first canonical path uniquely identifies each net in your schematics. It contains your design name, schematic folders, name, and other identifiers.
NODE_NAMEMarks the beginning of a node entry. The node name entry always ends with a semicolon after the node property list.
ReferenceThe reference of the physical part.
NumberThe pin number on the part attached to the net.
Canonical PathThe second canonical path uniquely identifies each part the net is attached to in your schematic pages. It contains your design name, schematic folders, ID, and other identifiers.
TypePin type of the pin attached to the net: input (I), output (O), bidirectional (IO), and so on.
Net PropertyAny property found in the property editor that is specified as a property to use in the configuration file, [netprops] section. Properties are separated by commas. The last property in the list is followed by a semicolon. There can by any number of properties. An example would be ECL=‘TRUE’;
occurrence_valueThe occurrence value of the property is given between the single quotation marks.

​ ### PSTXNET文件格式

FILE_TYPE=EXPANDEDNETLIST;
NET_NAME
'Name'
'Canonical Path';
NODE_NAME Reference Number
'Canonical Path':
'Type':;
Net Property='occurrence_value',
...
;
END.

PSTXNET样例

FILE_TYPE = EXPANDEDNETLIST;
{ Using PSTWRITER 14.0-p002 Oct-09-2000 at 10:32:05 }
NET_NAME
'N00011'
'@FULLADD.FULLADD(SCH_1):N00011':
C_
SIGNAL='@fulladd.fulladd(sch_1):n00011',
ECL='TRUE';
NODE_NAME U3 3
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679612@TTL.74LS04.NORMAL(CHIPS)':
'I':;
NODE_NAME U2 4
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679613@FULLADD.74LS08_0.NORMAL(CHIP
S)':
'I0':;
NODE_NAME U2 9
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679614@FULLADD.74LS08_0.NORMAL(CHIP
S)':
'I0':;
NODE_NAME U1 8
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679615@FULLADD.74LS32_0.NORMAL(CHIP
S)':
'O':;
NET_NAME
'SUM'
'@FULLADD.FULLADD(SCH_1):SUM':
C_
SIGNAL='@fulladd.fulladd(sch_1):sum';
NODE_NAME U1 6
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679615@FULLADD.74LS32_0.NORMAL(CHIP 
S)':
'O':;
NET_NAME
'X'
'@FULLADD.FULLADD(SCH_1):X':
C_
SIGNAL='@fulladd.fulladd(sch_1):x';
NODE_NAME U3 5
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679610@TTL.74LS04.NORMAL(CHIPS)':
'I':;
NODE_NAME U2 12
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679611@FULLADD.74LS08_0.NORMAL(CHI
PS)':
'I0':;
NODE_NAME U4 5
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679614@FULLADD.74LS08_0.NORMAL(CHI
PS)':
'I1':;
NET_NAME
'Y'
'@FULLADD.FULLADD(SCH_1):Y':
C_
SIGNAL='@fulladd.fulladd(sch_1):y';
NODE_NAME U3 9
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679612@TTL.74LS04.NORMAL(CHIPS)':
'I':;
NODE_NAME U4 1
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679613@FULLADD.74LS08_0.NORMAL(CHIP
S)':
'I0':;
NODE_NAME U4 4
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679614@FULLADD.74LS08_0.NORMAL(CHIP
S)':
'I0':;
NET_NAME
'CARRY_IN'
'@FULLADD.FULLADD(SCH_1):CARRY_IN':
C_
SIGNAL='@fulladd.fulladd(sch_1):carry_in';
NODE_NAME U3 1
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679610@TTL.74LS04.NORMAL(CHIPS)':
'I':;
NODE_NAME U2 1
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679611@FULLADD.74LS08_0.NORMAL(CHIP
S)':
'I0':;
NODE_NAME U2 10
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679614@FULLADD.74LS08_0.NORMAL(CHIP
S)':
'I1':;
NET_NAME
'N00013'
'@FULLADD.FULLADD(SCH_1):N00013':
C_
SIGNAL='@fulladd.fulladd(sch_1):n00013';
NODE_NAME U1 1
'@FULLADD.FULLADD(SCH_1):I505679590@FULLADD.74LS32_0.NORMAL(CHIPS)':
'I0':; 
NODE_NAME U2 8
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679614@FULLADD.74LS08_0.NORMAL(CHIP
S)':
'O':;
NET_NAME
'N00023'
'@FULLADD.FULLADD(SCH_1):N00023':
C_
SIGNAL='@fulladd.fulladd(sch_1):n00023';
NODE_NAME	U1 2
'@FULLADD.FULLADD(SCH_1):I505679590@FULLADD.74LS32_0.NORMAL(CHIPS)':
'I1':;
NODE_NAME U4 6
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679614@FULLADD.74LS08_0.NORMAL(CHIP
S)':
'O':;
NET_NAME
'CARRY_OUT'
'@FULLADD.FULLADD(SCH_1):CARRY_OUT':
C_
SIGNAL='@fulladd.fulladd(sch_1):carry_out';
NODE_NAME	U1 3
'@FULLADD.FULLADD(SCH_1):I505679590@FULLADD.74LS32_0.NORMAL(CHIPS)':
'O':;
NET_NAME
'X_BAR'
'@FULLADD.FULLADD(SCH_1):X_BAR':
C_
SIGNAL='@fulladd.fulladd(sch_1):x_bar';
NODE_NAME U3 2
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679610@TTL.74LS04.NORMAL(CHIPS)':
'O':;
NODE_NAME U2 5
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679613@FULLADD.74LS08_0.NORMAL(CHIP
S)':
'I1':;
NET_NAME
'N5056796111'
'@FULLADD.FULLADD(SCH_1):N5056796111':
C_
SIGNAL='@fulladd.fulladd(sch_1):n5056796111';
NODE_NAME U2 2
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679611@FULLADD.74LS08_0.NORMAL(CHIP
S)':
'I1':;
NODE_NAME U3 4
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679612@TTL.74LS04.NORMAL(CHIPS)':
'O':;
NET_NAME
'N00032'
'@FULLADD.FULLADD(SCH_1):N00032':
C_
SIGNAL='@fulladd.fulladd(sch_1):n00032';
NODE_NAME U2 3
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679611@FULLADD.74LS08_0.NORMAL(CHIP
S)':
'O':;
NODE_NAME U1 4
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679615@FULLADD.74LS32_0.NORMAL(CHIP
S)': 
'I0':;
NET_NAME
'N00034'
'@FULLADD.FULLADD(SCH_1):N00034':
C_
SIGNAL='@fulladd.fulladd(sch_1):n00034';
NODE_NAME U1 5
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679615@FULLADD.74LS32_0.NORMAL(CHIP
S)':
'I1':;
NODE_NAME U2 6
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679613@FULLADD.74LS08_0.NORMAL(CHIP
S)':
'O':;
NET_NAME
'X_BAR_74'
'@FULLADD.FULLADD(SCH_1):X_BAR_74':
C_
SIGNAL='@fulladd.fulladd(sch_1):x_bar_74';
NODE_NAME U3 6
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679610@TTL.74LS04.NORMAL(CHIPS)':
'O':;
NODE_NAME U4 2
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679613@FULLADD.74LS08_0.NORMAL(CHIP
S)':
'I1':;
NET_NAME
'N5056796111_76'
'@FULLADD.FULLADD(SCH_1):N5056796111_76':
C_
SIGNAL='@fulladd.fulladd(sch_1):n5056796111_76';
NODE_NAME U2 13
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679611@FULLADD.74LS08_0.NORMAL(CHIP
S)':
'I1':;
NODE_NAME U3 8
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679612@TTL.74LS04.NORMAL(CHIPS)':
'O':;
NET_NAME
'N00032_77'
'@FULLADD.FULLADD(SCH_1):N00032_77':
C_
SIGNAL='@fulladd.fulladd(sch_1):n00032_77';
NODE_NAME U2 11
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679611@FULLADD.74LS08_0.NORMAL(CHIP
S)':
'O':;
NODE_NAME U1 9
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679615@FULLADD.74LS32_0.NORMAL(CHIP
S)':
'I0':;
NET_NAME
'N00034_79'
'@FULLADD.FULLADD(SCH_1):N00034_79':
C_
SIGNAL='@fulladd.fulladd(sch_1):n00034_79';
NODE_NAME U1 10
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679615@FULLADD.74LS32_0.NORMAL(CHIP
S)': 
'I1':;
NODE_NAME U4 3
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679613@FULLADD.74LS08_0.NORMAL(CHIP
S)':
'O':;
END.

PSTXPRT.DAT

The PSTXPRT.DAT file (the expanded part list) lists each reference designator and the sections assigned to it. The PSTXPRT.DAT file is ordered by reference designator and section number.

PSTXPRT.DAT文件元素

PSTXPRT.DAT sectionDescription
DIRECTIVESMarks the beginning of the directives section. Directives always end with a semicolon.
PST_VERSIONVersion of PCB Editor interface.
ROOT_DRAWINGRoot schematic folder of design in Capture.
POST_TIMEDate and time of netlist.
SOURCE_TOOLTool used is Capture Writer or Design Entry HDL Writer.
END_DIRECTIVESMarks the end of the Directives section.
Part ReferenceThe reference designator name of the physical part.
ComponentInstancePropertyProperties and values of any component instance (package) properties found on the part and listed in the configuration file under the [ComponentInstanceProperty] section.
PART NAMEConcatenation of Source Package, PCB Footprint, and other properties found in the [ComponentDefinitionProps] section of the configuration file used for netlisting.
SECTION_NUMBER #Marks the beginning of a physical section number. Each section of the package used gets its own section number. Single section parts have only one section number.
Canonical pathThe canonical path uniquely identifies each part in your schematic pages. It contains your design name, schematicfolders, part ID, source part, implementation type, and other identifiers.
Physical pathThe physical path uniquely identifies each part in a design. The physical path contains the design name, schematic folder, page number, part ID, source part, implementation type, and other identifiers specific to the selected part in the design.
Part (function) propertyAny property found in the property editor that is specified as a property to use in the configuration file, [functionprops] section.Properties are separated by commas. The last property in the list is followed by a semicolon. There can by any number of properties.
occurrence_valueThe occurrence value of the property is given between the single quotation marks.
PRIM_FILELocation of the where package properties are listed. This is the PSTCHIP.DAT file which is closely linked to the PSTXPRT.DAT file.
designatorThe designator is now stored so that we know if designators are numeric or alphabetic.

PSTXPRT.DAT文件格式

FILE_TYPE = EXPANDEDPARTLIST;
DIRECTIVES
PST_VERSION='PST_HDL_CENTRIC_VERSION_0';
ROOT_DRAWING = 'Root schematic folder of design' ;
POST_TIME = 'Date and Time of Netlist' ;
SOURCE_TOOL='Capture_Writer';
END_DIRECTIVES ;
PART_NAME
Part Reference ’PART NAME’;
ComponentInstanceProperty='occurence_value';
.
.
SECTION_NUMBER #
'Canonical path',
'Physical path',
Part(function) property='occurrence_value',
.
.
.
PRIM_FILE='.\pstchip.dat',
SECTION='designator';
END.

PSTXPRT.DAT文件样例

FILE_TYPE = EXPANDEDPARTLIST;
{ Using PSTWRITER 16.5.0 p001Apr-05-2011 at 10:09:06 }
DIRECTIVES
PST_VERSION='PST_HDL_CENTRIC_VERSION_0';
ROOT_DRAWING='FULLADD';
POST_TIME='Mar 29 2011 00:05:38';
SOURCE_TOOL='CAPTURE_WRITER';
END_DIRECTIVES;
PART_NAME
U1 'ORGATE':;
SECTION_NUMBER 1
'@FULLADD.FULLADD(SCH_1):I505679590@FULLADD.74LS32.NORMAL(CHIPS)':
C_PATH='@fulladd.fulladd(sch_1):i505679590@fulladd.\74ls32.normal\(chips)',
P_PATH='@fulladd.fulladd(sch_1):page1_i505679590@fulladd.\74ls32.normal\(chips)',
PRIM_FILE='.\pstchip.dat',
SECTION='A';
SECTION_NUMBER 2
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679615@FULLADD.74LS32.NORMAL(CHIPS
)': 
C_PATH='@fulladd.fulladd(sch_1):halfadd_a@fulladd.halfadd(sch_1):i505679615@fulladd.\74ls32.norm
al\(chips)',
P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_a@fulladd.halfadd(sch_1):page2_i505679615@fulladd.
\74ls32.normal\(chips)',
PRIM_FILE='.\pstchip.dat',
SECTION='B';
SECTION_NUMBER 3
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679615@FULLADD.74LS32.NORMAL(CHIPS
)':
C_PATH='@fulladd.fulladd(sch_1):halfadd_b@fulladd.halfadd(sch_1):i505679615@fulladd.\74ls32.norm
al\(chips)',
P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_b@fulladd.halfadd(sch_1):page2_i505679615@fulladd.
\74ls32.normal\(chips)',
PRIM_FILE='.\pstchip.dat',
SECTION='C';
PART_NAME
U2 'ANDGATE':;
SECTION_NUMBER 1
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679611@FULLADD.74LS08.NORMAL(CHIPS
)':
C_PATH='@fulladd.fulladd(sch_1):halfadd_a@fulladd.halfadd(sch_1):i505679611@fulladd.\74ls08.norm
al\(chips)',
P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_a@fulladd.halfadd(sch_1):page2_i505679611@fulladd.
\74ls08.normal\(chips)',
PRIM_FILE='.\pstchip.dat',
SECTION='A';
SECTION_NUMBER 2
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679613@FULLADD.74LS08.NORMAL(CHIPS
)':
C_PATH='@fulladd.fulladd(sch_1):halfadd_a@fulladd.halfadd(sch_1):i505679613@fulladd.\74ls08.norm
al\(chips)',
P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_a@fulladd.halfadd(sch_1):page2_i505679613@fulladd.
\74ls08.normal\(chips)',
PRIM_FILE='.\pstchip.dat',
SECTION='B';
SECTION_NUMBER 3
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679614@FULLADD.74LS08.NORMAL(CHIPS
)':
C_PATH='@fulladd.fulladd(sch_1):halfadd_a@fulladd.halfadd(sch_1):i505679614@fulladd.\74ls08.norm
al\(chips)',
P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_a@fulladd.halfadd(sch_1):page2_i505679614@fulladd.
\74ls08.normal\(chips)',
PRIM_FILE='.\pstchip.dat',
SECTION='C';
SECTION_NUMBER 4
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679611@FULLADD.74LS08.NORMAL(CHIPS
)':
C_PATH='@fulladd.fulladd(sch_1):halfadd_b@fulladd.halfadd(sch_1):i505679611@fulladd.\74ls08.norm
al\(chips)', 
P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_b@fulladd.halfadd(sch_1):page2_i505679611@fulladd.
\74ls08.normal\(chips)',
PRIM_FILE='.\pstchip.dat',
SECTION='D';
PART_NAME
U3 'NOTGATE':;
SECTION_NUMBER 1
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679610@FULLADD.74LS04.NORMAL(CHIPS
)':
C_PATH='@fulladd.fulladd(sch_1):halfadd_a@fulladd.halfadd(sch_1):i505679610@fulladd.\74ls04.norm
al\(chips)',
P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_a@fulladd.halfadd(sch_1):page2_i505679610@fulladd.
\74ls04.normal\(chips)',
PRIM_FILE='.\pstchip.dat',
SECTION='A';
SECTION_NUMBER 2
'@FULLADD.FULLADD(SCH_1):HALFADD_A@FULLADD.HALFADD(SCH_1):I505679612@FULLADD.74LS04.NORMAL(CHIPS
)':
C_PATH='@fulladd.fulladd(sch_1):halfadd_a@fulladd.halfadd(sch_1):i505679612@fulladd.\74ls04.norm
al\(chips)',
P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_a@fulladd.halfadd(sch_1):page2_i505679612@fulladd.
\74ls04.normal\(chips)',
PRIM_FILE='.\pstchip.dat',
SECTION='B';
SECTION_NUMBER 3
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679610@FULLADD.74LS04.NORMAL(CHIPS
)':
C_PATH='@fulladd.fulladd(sch_1):halfadd_b@fulladd.halfadd(sch_1):i505679610@fulladd.\74ls04.norm
al\(chips)',
P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_b@fulladd.halfadd(sch_1):page2_i505679610@fulladd.
\74ls04.normal\(chips)',
PRIM_FILE='.\pstchip.dat',
SECTION='C';
SECTION_NUMBER 4
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679612@FULLADD.74LS04.NORMAL(CHIPS
)':
C_PATH='@fulladd.fulladd(sch_1):halfadd_b@fulladd.halfadd(sch_1):i505679612@fulladd.\74ls04.norm
al\(chips)',
P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_b@fulladd.halfadd(sch_1):page2_i505679612@fulladd.
\74ls04.normal\(chips)',
PRIM_FILE='.\pstchip.dat',
SECTION='D';
PART_NAME
U4 'ANDGATE':;
SECTION_NUMBER 1
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679613@FULLADD.74LS08.NORMAL(CHIPS
)': 
C_PATH='@fulladd.fulladd(sch_1):halfadd_b@fulladd.halfadd(sch_1):i505679613@fulladd.\74ls08.norm
al\(chips)',
P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_b@fulladd.halfadd(sch_1):page2_i505679613@fulladd.
\74ls08.normal\(chips)',
PRIM_FILE='.\pstchip.dat',
SECTION='A';
SECTION_NUMBER 2
'@FULLADD.FULLADD(SCH_1):HALFADD_B@FULLADD.HALFADD(SCH_1):I505679614@FULLADD.74LS08.NORMAL(CHIPS
)':
C_PATH='@fulladd.fulladd(sch_1):halfadd_b@fulladd.halfadd(sch_1):i505679614@fulladd.\74ls08.norm
al\(chips)',
P_PATH='@fulladd.fulladd(sch_1):page1_halfadd_b@fulladd.halfadd(sch_1):page2_i505679614@fulladd.
\74ls08.normal\(chips)',
PRIM_FILE='.\pstchip.dat',
SECTION='B';
END.

​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

U.2 SSD
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