1.问题描述:
Error detected by hpeesofsim during netlist parsing.
A global’ statement in subcircuit DC-SP-1_stage_symbol’ lists node vss!’ as a global node,
but that node is not listed on a global’ or globalnodes’ statement at the top level.
2.电路描述
下图为ADS LoadPull模板,将晶体管替换成自己的电路,除修改变量频率、电压、输入功率外,其他保持不变
我这里用的是TSMC的工艺,在DC-SP-1_stage_symbol电路内,放置了TSMC工艺库控件,而没有在上图放置,从而导致了报错。
3.解决方案
把TSMC工艺库控件 从 DC-SP-1_stage_symbol内,转移到主电路图,即第一幅图内即可。