题目:设计一个串行数据检测器。要求是:连续4个或4个以上为1时输出为1,其他输入情况下为0。
代码如下:
module four_one( x, z, clk, rst, state);
input x, clk, rst;
output z;
output[2:0] state;
reg[2:0] state;
wire z;
parameter
IDLE = 'd0,
A = 'd1,
B = 'd2,
C = 'd3,
D = 'd4;
assign z = (state == D) ? 1 : 0;
always @(posedge clk or negedge rst)
if (!rst)
begin
state <= IDLE;
end
else
casex (state)
IDLE: if (x == 1)
begin
state <= A;
end
else
begin
state <= IDLE;
end
A: if (x == 1)
begin
state <= B;
end
else
begin
state <= IDLE;
end
B: if (x == 1)
begin