6.1.2 The continuous assignment statement

Frm: IEEE Std 1364™-2001, IEEE Standard Verilog® Hardware Description Language

The continuous assignment statement shall place a continuous assignment on a net data type. The net may be explicitly declared, or may inherit an implicit declaration in accordance with the implicit declarations rules defined in 3.5.

Assignments on nets shall be continuous and automatic. This means that whenever an operand in the righthand side expression changes value, the whole right-hand side shall be evaluated and if the new value is different from the previous value, then the new value shall be assigned to the left-hand side.

Example:

Example 1—The following is an example of a continuous assignment to a net that has been previously declared:

wire mynet ;
assign (strong1, pull0) mynet = enable ;

 Example 2—The following is an example of the use of a continuous assignment to model a 4-bit adder with carry. The assignment could not be specified directly in the declaration of the nets because it requires a concatenation on the left-hand side.

module adder (sum_out, carry_out, carry_in, ina, inb);
output [3:0] sum_out;
output carry_out;
input [3:0] ina, inb;
input carry_in;
wire carry_out, carry_in;
wire [3:0] sum_out, ina, inb;
assign {carry_out, sum_out} = ina + inb + carry_in;
endmodule

 Example 3—The following example describes a module with one 16-bit output bus. It selects between one of four input busses and connects the selected bus to the output bus.

module select_bus(busout, bus0, bus1, bus2, bus3, enable, s);
parameter n = 16;
parameter Zee = 16’bz;
output [1:n] busout;
input [1:n] bus0, bus1, bus2, bus3;
input enable;
input [1:2] s;
tri [1:n] data; // net declaration
// net declaration with continuous assignment
tri [1:n] busout = enable ? data : Zee;
// assignment statement with four continuous assignments
assign
data = (s == 0) ? bus0 : Zee,
data = (s == 1) ? bus1 : Zee,
data = (s == 2) ? bus2 : Zee,
data = (s == 3) ? bus3 : Zee;
endmodule

The following sequence of events is experienced during simulation of this example:

a) The value of s, a bus selector input variable, is checked in the assign statement. Based on the value of s, the net data receives the data from one of the four input buses.

b) The setting of data net triggers the continuous assignment in the net declaration for busout. If enable is set, the contents of data are assigned to busout; if enable is 0, the contents of Zee are assigned to busout.

 

转载于:https://www.cnblogs.com/qiyuexin/p/6384557.html