FPGA内部信号避免高阻态

RT，否则警告Warning: Tri-state node(s) do not directly drive top-level pin(s)，会利用或门代替中间的扇出fan-out.

原因：在进行FPGA设计时，对于FPGA内部的信号不能出现被赋值为高阻的状态，只有顶层的信号，即输出的信号才可以赋值为高阻态。

找出这个信号，然后把赋值为x'bz改为x'b0或x'b1(具体是改为x'b0还是x'b1要根据实际情况确定,x也行)。

CAUSE: The design contains tri-state nodes that drive non-tri-state logic, but the chip does not support internal tri-states. As a result, the Quartus II software converts all the tri-state nodes feeding internal logic to an equivalent logic.

ACTION: Avoid this warning by either removing the non-tri-state fan-outs of the affected tri-state nodes or replacing the tri-state nodes with non-tri-state logic.

实例：

module tri_state (input oe1, data1, in, output out, output bidir);

wire tribuf;

assign tribuf = oe1 ? data1 : 1'