VHDL中attribute keep of xxx: signal is "true";的用法

attribute keep of error_channelb: signal is "true"; 

用法就是 keep a signal after mapping; 如果要用chipscope和在ucf文件中直接使用信号名的,可用keep这保持,这样可方便我们添加观察信号和添加约束.

 

Often you want to assign a constraint to a particular signal in your design, or you want be able to find a particular signal in Chipscope inserter. In both cases, the signal must be in the physical design database (ie. in the .NCD file – Native Circuit Description) which is generated by the mapper. Not all signal names in your HDL code will end up in the NCD, some of them will be absorbed into logic blocks and grouped into a different signal name. To ensure that a particular signal name ends up in the NCD, it’s important to use the “keep” signal constraint.

When a design is mapped, some nets may be absorbed into logic blocks. The mapping tool does this because as a signal passes from one logic block to anoth