global clock network

1. handbook:

Cyclone II devices provide a global clock network and up to four
phase-locked loops (PLLs). The global clock network consists of up to 16
global clock lines that drive throughout the entire device. The global clock
network can provide clocks for all resources within the device, such as
input/output elements (IOEs), LEs, embedded multipliers, and
embedded memory blocks. The global clock lines can also be used for
other high fan-out signals.

2.http://blog.chinaaet.com/detail/28569.html

讲到cmos_pclk 输出口直接连到FPGA全局时钟上面，。。。， 电路变得很稳定，图像变得很清晰，不在偏移，perfect

我的cmos_pclk 也这么用了。其实USB IFCLK也可以这么用。

3。待续

转载于:https://www.cnblogs.com/winkle/p/3189722.html