FPGA clock network architecture: Flexibility vs. Area and Power (paper)

最新推荐文章于 2024-03-25 20:57:50 发布

zhangxlubc

最新推荐文章于 2024-03-25 20:57:50 发布

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分类专栏： FPGA

本文链接：https://blog.csdn.net/zhangxlubc/article/details/84891719

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本文介绍了商业FPGA的时钟网络结构，包括Altera Strataix II和Xilinx Virtex II Pro的全球和局部时钟网络。讨论了全交叉bar和集中器网络，并提出了一种参数化的时钟网络模型，该模型采用三级时钟分布拓扑。总结指出，在逻辑块、肋骨和脊中增加时钟输入的数量对面积和功率的影响不同，需要权衡。

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commercial clock networks:

current commercial FPGA support multiple and local and global clock domains. the FPGA is divided into four quadrants.

Altera Straitix II provides 16 global clock signals, which can be connected to all the FFs on the FPGA, and 8 local clock networks in each of four quadrant, which can be connected to all the FFs within the quadrant.

Xilinx Virtex II Pro devices provide 16 global clock networks and 8 locak clock networks, unlike Altera devices, however, the global clocks in the Virtex II Pro are not connected to FFs directly, instead, the global clocks drive local clocks within each quadrant.

within a quadrant, the clocks are distributed to rows of logic blocks through a row MUX and rib routing channels.

in Stratix II devices, each row MUX chooses 6 clocks from 16+8 clocks and provides them to all FFs in that row:

in Virtex II devices, the row MUX choose between 8 local clocks.

the circuits that drive the clock networks are similar between the above two, and can be driven by external source, internal source, or by clock management circuits (e.g. PLL).