RST_n的问题

有一个灰常郁闷的问题。。。

module CLK_Generater(
                    input        CLOCK_100,
                    input        RST_n,
                    input        Key,
                    output    reg    [3:0]    CLK_DivChoose,

                    );
reg     [19:0]    count;            //Delay_10ms
reg             CLK_100Hz;         //100HZ(10ms)时钟信
reg     [2:0]    state;          //状态标志

reg        [16:0]    cnt;
reg        [17:0]    Div_cnt;

always @(posedge CLOCK_100 or negedge RST_n)
begin
    if(!RST_n)
        begin
        CLK_100Hz<=0;
        count<=0;
        end
    else
        begin
        if(count<20'd1000000)
            begin
            count<=count+1'b1;
            CLK_100Hz<=CLK_100Hz;
            end
        else
            begin
            count<=0;
            CLK_100Hz<=~CLK_100Hz;
            end   
        end
end

always@(posedge CLK_100Hz or negedge RST_n)
begin
    if(!RST_n)
        CLK_DivChoose <= 4'h0;
    else
        begin
        case(state)                //按键，不按下去的时候是VCC高，按下去的时候是GND低
        0:
            begin
            if(!Key)            //检测键盘是否被按下(Delay_5ms)
                state <= 1;
            else
                state <= 0;        //未按下，循环检测
            end
        1:
            begin
            if(!Key)            //检测键盘是否真的被按下，还是抖动(消抖动(Delay_5ms))
                state <= 2;        //检测到不是抖动，进行下一步操作
            else
                state <= 0;        //是抖动，回去继续检测按键
            end
        2:
            begin           
            CLK_DivChoose <= CLK_DivChoose+1'b1;
            state <= 3;            //只进行加1操作，不连加           
            end
        3:
            begin
            if(Key)                //松手(VCC)检测，有可能是抖动
                state <= 4;
            else                //检测到还是(GND)低电平，未松手
                state <= 3;
            end
        4:
            begin
            if(Key)                //松手(VCC)检测，有可能是抖动
                state <= 0;
            else
                state <= 4;        //检测到还是(GND)低电平，未松手
            end
        endcase
        end
end

endmodule

CLK_DivChoose 同时接到4个LED

转载于:https://www.cnblogs.com/FPGA_DSP/archive/2011/02/09/1950416.html