usb30 fpga slavefifo interface

参照AN65974-AN61345-AN84868

 A0:A1:  the address signals A0:A1 on the interface indicate the thread to be accessed. FX3’s DMA fabric then routes the
data to the socket mapped to that thread. Therefore, in this example, when A0:A1 = 0, thread 0 is accessed, and any data that
is transferred over thread 0 is routed to socket 2. Similarly, when A0:A1 = 1, data is transferred in and out of socket 3.

FLAGA,FLAGB: Flags indicate empty or full, based on the direction of the socket (configured during socket initialization). Therefore, the flag
indicates empty/not empty status if data is being read out of the socket and indicates full/not full status if data is being written
into the socket.

PCLK(IFCLK): 可以达到100mhz,

Synchronous Slave FIFO Write Sequence: the value on the data bus is written into the FIFO on every rising edge of PCLK

转载于:https://www.cnblogs.com/winkle/archive/2013/03/11/2954598.html