Abstract
$skew是Verilog所提供的專門用來做timing check的system task,可以檢查兩個信號間最大的延遲,若兩個信號間的skew大於我們所指定的需求,將產生violation warning。
Introduction
使用環境:NC-Verilog 5.4 + Debussy 5.4
如下圖所示,若兩個信號之間的skew大於limit時,將產生violation warning。
Testbench
skew_tb.v / Verilog
1
/*
2 (C) OOMusou 2009 http://oomusou.cnblogs.com
3
4 Filename : skew_tb.v
5 Compiler : NC-Verilog 5.4 + debussy 5.4
6 Description : $skew demo
7 Release : 07/15/2009 1.0
8 */
9 `timescale 1ns / 1ns
10
11 module skew_tb;
12
13 reg reg_a;
14 reg reg_b;
15
16 wire wire_a;
17 wire wire_b;
18
19 assign wire_a = reg_a;
20 assign wire_b = reg_b;
21
22 initial begin
23 $fsdbDumpfile( " skew_tb.fsdb " );
24 $fsdbDumpvars( 0 , skew_tb);
25 # 50 ;
26 $finish;
27 end
28
29 initial begin
30 reg_a = 1 ' b0;
31 reg_b = 1 ' b0;
32 # 10 ;
33 reg_a = 1 ' b1;
34 # 4 ;
35 reg_a = 1 ' b0;
36 # 1 ;
37 reg_b = 1 ' b1;
38 # 4 ;
39 reg_b = 1 ' b0;
40 end
41
42 specify
43 $skew( posedge wire_a, posedge wire_b, 4 ); /* 6 is ok */
44 endspecify
45
46 endmodule
2 (C) OOMusou 2009 http://oomusou.cnblogs.com
3
4 Filename : skew_tb.v
5 Compiler : NC-Verilog 5.4 + debussy 5.4
6 Description : $skew demo
7 Release : 07/15/2009 1.0
8 */
9 `timescale 1ns / 1ns
10
11 module skew_tb;
12
13 reg reg_a;
14 reg reg_b;
15
16 wire wire_a;
17 wire wire_b;
18
19 assign wire_a = reg_a;
20 assign wire_b = reg_b;
21
22 initial begin
23 $fsdbDumpfile( " skew_tb.fsdb " );
24 $fsdbDumpvars( 0 , skew_tb);
25 # 50 ;
26 $finish;
27 end
28
29 initial begin
30 reg_a = 1 ' b0;
31 reg_b = 1 ' b0;
32 # 10 ;
33 reg_a = 1 ' b1;
34 # 4 ;
35 reg_a = 1 ' b0;
36 # 1 ;
37 reg_b = 1 ' b1;
38 # 4 ;
39 reg_b = 1 ' b0;
40 end
41
42 specify
43 $skew( posedge wire_a, posedge wire_b, 4 ); /* 6 is ok */
44 endspecify
45
46 endmodule
NC-Verilog產生Timing violation的warning
兩個信號間的skew為5 ns
42行
specify
$skew( posedge wire_a, posedge wire_b, 4 ); /* 6 is ok */
endspecify
$skew( posedge wire_a, posedge wire_b, 4 ); /* 6 is ok */
endspecify
使用$skew檢查timing,以上表示從posedge wire_a到posedge wire_b間的skew limit為4 ns,若skew大於4 ns,將產生timing violation warning。此外,Verilog規定timing check類的system task,一定要放在specify block內。
完整程式碼下載
s_skew.7z
Reference
Verilog延時specify
Cadence NC-Verilog Simulator Help
See Also
(筆記) 如何使用$width? (SOC) (Verilog)