Verilog系统任务和函数（Tasks and Functions）

Verilog系统任务和函数（Tasks and Functions）

常用系统任务和函数列表如下： 

- Display tasks 

- File I/O tasks 

- Timescale tasks 

- Simulation control tasks 

- Timing check tasks 

- Simulation time functions 

- Real conversion functions 

- Random functions

Display tasks 

System display tasks write text to the standard output or a file.

Syntax:

$display([ mcd, ] "text", signal, signal, ...);
$write( [ mcd, ] "text", signal, signal, ...);
$strobe( [ mcd, ] "text", signal, signal, ...);
$monitor( [ mcd, ] "text", signal, signal, ...);

mcd = expression       // multi-channel descriptor

Description:

$display and $write prints the text when the statement is executed during simulation. The only difference between the two is that $display writes out a newline character at the end of the text, whereas $write does not.

$strobe prints the text when all simulation events in the current time step have executed. A newline is automatically added to the text.

$monitor prints the text whenever one of the signals in the signal list changes. A newline is automatically added to the text.

The text may contain format specifiers. If so, each text must be followed by enough signals to provide values for all the format specifiers. The following format specifiers are allowed in the text:

%b or %B	Binary format
%d or %D	Decimal format (default)
%h or %H	Hexadecimal format
%o or %O	Octal format
%e or %E	Real in exponential format
%f or %F	Real in decimal format
%g or %G	Real in decimal or exponential format (shortest result)
%c or %C	Character
%s or %S	String
%t or %T	Time format
%m or %M	Hierarchical name
%v or %V	Net signal strength

After the % character a minimum field width value may be include (e.g. %6d). A minimum field width of zero means that the field will always be just big enough to display the value. The %e and %f may specify the field width for both sides of the decimal point (e.g. %6.2f).

The text may also include the following escaped characters:

\n	Newline
\t	Tab
\\	Backslash
\ddd	Octal code
%%	Percent sign

If the signal list contains two adjacent commas, a space is written out at that point.

Example:

$display("The binary value of A is: %b", A);
$write("The register values are: ", Reg1,, Reg2,, Reg3, "\n");

initial begin
  A = 0;
  $display(A);      // displays 0
  $strobe(A);       // displays 1
  A = 1;
end

Notes:

• Only one $monitor process can be running simultaneously.

File I/O tasks 

System file I/O tasks are used for files on disk.

Syntax:

mcd = $fopen("file_name" [ , type ] );
$fclose(mcd);
$readmemb("file_name", memory_name [ , start_address [ , end_address ]] );
$readmemh("file_name", memory_name [ , start_address [ , end_address ]] );
c = $fgetc(mcd);
ungetc(c, mcd);
i = $fgets(str, mcd);
i = $fscanf(mcd, "text", signal, signal, ...);
i = $sscanf(str, "text", signal, signal, ...);
i = $fread(reg_or_mem, mcd [ , start_address [ , end_address ]] );i = $ftell(mcd);
i = $fseek(mcd, offset, operation);
i = $rewind(mcd);
$fflush( [ mcd ] );
i = $ferror(mcd, str);
$swrite(output_reg, signal, signal, ...));
$sformat(output_reg, text", signal, signal, ...); 

mcd = expression       // multi-channel descriptor; in Verilog-2001 file descriptor

Description:

$fopen opens a disk file for writing, and returns a 32-bit unsigned integer multi-channel descriptor pointer to the file. It returns a zero if the file could not be opened for writing. In Verilog-2001 the type indicates how the file is to be opened. The "b" distinguishes a binary file from a text file:

Type	Description
"r" or "rb"	Open for reading
"w" or "wb"	Create for writing
"a" or "ab"	Append
"r+" or "rb+" or "r+b"	Open for update (reading and writing)
"w+" or "wb+" or "w+b"	Create for update
"a+" or "ab+" or "a+b"	Append; open or create for update at end-of-file

$fclose closes a disk file that was opened by $fopen.

$readmemb and $readmemh initialize a memory array with the values from the file. The file must be an ASCII file with values represented in binary ($readmemb) or hexadecimal ($readmemh). The data values must be the same width as the memory array, and be separated by white spaces. The start and end address are hexadecimal numbers, even for $readmemb, preceded by @.

Verilog-2001 adds several new reading tasks: $fgetc reads a byte (a character) from the file. $fgets reads a line from the file. $fscanf and $sscanf reads data and interprets the data according to a format. $fscanf reads the data from a file whereas $sscanf reads the data from a reg variable. $fread reads binary data from the file. $ungetc inserts a specified character into a buffer specified by the file.

Other new Verilog-2001 file I/O tasks are: $ftell returns the offset from the beginning of the file. $fseek sets the position of the next input or output operation on the file. $rewind is the same as $fseek(0,0). $fflush writes any buffered output to the file. $ferror can be used to obtain more information about an error. $swrite and $sformat writes a string to a reg variable. $sformat interprets the string as a format string.

The system display tasks can be used to write to a file.

Example:

initial begin
  File = $fopen("Result.dat");
  if (!File)
    $display("Could not open \"result.dat\"");
  else begin
    $display(File, "Result is: %4b", A);
    $fclose(File);
  end
end

reg [7:0] Memory [15:0];
initial begin
  $readmemb("Stimulus.txt", Memory);
end

Timescale tasks

System file I/O tasks are used for simulation time formatting.

Syntax:

$printtimescale [ (hierarchical_name) ];
$timeformat [ (unit, precision, "suffix", min_field_width) ];

Description:

$printtimescale displays the time scale of the specified module. When no hierarchical name is specified, it displays the time scale of the module that is in the current scope.

$timeformat defines the format used by the %t text format specifier. Unit is an integer between 0 and -15 and defines the base that time is to be displayed:

0 = 1 sec	-4 = 100 us	-8 = 10 ns	-12 = 1 ps
-1 = 100 ms	-5 = 10 us	-9 = 1 ns	-13 = 100 fs
-2 = 10 ms	-6 = 1 us	-10 = 100 ps	-14 = 10 fs
-3 = 1 ms	-7 = 100 ns	-11 = 10 ps	-15 = 1 fs

Precision is the number of decimal digits to display. Suffix is a string appended to the time. Min field width is the minimum number of characters that will be displayed.

The defaults are used if no arguments are specified for $timeformat. The default unit is the simulation precision; precision is 0; suffix is the null string; min_field_width is 20 characters.

Example:

$printtimescale(top.u1);
$timeformat(-9, 2 " ns", 15);

Simulation control tasks

System simulation control tasks control the simulation.

Syntax:

$finish [ (n) ];
$stop [ (n) ]

n = 0 | 1 | 2

Description:

$finish finishes a simulation and exits the simulation process. If an argument is supplied, diagnostic messages are printed as follows:

0. prints nothing
1. prints simulation time and location
2. prints simulation time, location and statistics about the used memory and CPU time

$stop suspends the simulation. The argument determines the type of diagnostic messages produced. 0 gives the least amount, 2 gives the most amount of output.

Example:

$finish(2);
$stop;

Timing check tasks

System timing check tasks are used in specify blocks to perform common timing checks.

Syntax:

$setup(data_event, reference_event, limit [ , notifier ] );
$hold(reference_event, data_event, limit [ , notifier ] );
$setuphold(reference_event, data_event, setup_limit, hold_limit [ , notifier ] 
    [, tstamp_cond ] [ , tcheck_cond ] [ , delayed_ref ] [ , delayed_data ] );
$period(reference_event, limit [ , notifier ] );
$width(reference_event, limit [ , treshold [ , notifier ]] );
$skew(reference_event, data_event, limit [ , notifier ] );
$recovery(reference_event, data_event, limit [ , notifier ] );
$nochange(reference_event, data_event, start_edge_offset, end_edge_offset [ , notifier ] ); 
$removal(reference_event, data_event, limit [ , notifier ]
$recrem(control_event, data_event, recovery_limit, removal_limit [ , notifier ] 
	[ , tstamp_cond ] [ , tcheck_cond ] [ , delayed_clk ] [ , delayed_data ];
$timeskew(reference_event, data_event, limit [ , notifier ] [ , event_based_flag ] [ , remain_active_flag ];
$fullskew(reference_event, data_event, limit [ , notifier ] [ , event_based_flag ] [ , remain_active_flag ];

Description:

System timing checks may only be used in specify blocks and perform common timing checks.

A transition on the reference event (input signal) establishes a reference time for changes on the data event. A transition on the data event (input signal) initiates the timing check. The limit and treshold are delay values. The notifier is a reg variable. When a timing violation occurs, the model functionality can use the notifier flag to modify the outputs.

Tstamp_cond places a condition on the stamp event. Tcheck_cond places a condition on the check event. Delayed_ref and delayed_clk are a delayed version of the reference signal. Delayed_data is a delayed version of the data signal. The delays are used for negative timing checks.

Example:

specify 
  specparam TSetup = 2.5, THold = 1.3;
  $setup(Data, posedge Clk, TSetup);
  $hold(posedge Clk, Data, THold);
  $width(negedge Clk, 10.5, 0.5);
endspecify 

Notes:

• The reference event must be an edge triggered statement for $nochange, $period, $recovery and $width.
• The reference event may use the keyword edge, except for $nochange and $recovery, where onlyposedge and negedge are allowed.

Simulation time functions

System simulation time functions return the current simulation time.

Syntax:

$time;
$stime;
$realtime;

Description:

$time returns the current simulation time as a 64-bit unsigned integer.

$stime returns the lower 32-bits of the current simulationt time as an unsigned integer.

$realtime returns the current simulation time as a real number.

Example:

$display("Current simulation time is: ", $time);

Real conversion functions

System real conversion functions are conversion functions for real numbers.

Syntax:

$realtobits(real_value);
$bitstoreal(bit_value);
$rtoi(real_value);
$itor(integer_value);

Description:

$realtobits converts a real number to a 64-bit representation, so that a real number can be passed through the port of a module.

$bitstoreal converts the bit value to a real number.

$rtoi converts a real number to an integer. It truncates the real number to form the integer.

$itor converts an integer to a real value.

Example:

reg [63:0] A;
real B;
B = $bitstoreal(A);
integer C = 14;
B = $itor(C);       // B = 14.0

Random functions

System random functions generate a random number.

Syntax:

$random [ (seed) ];
$dist_chi_square(seed, degree_of_freedom);
$dist_erlang(seed, k_stage, mean);
$dist_exponential(seed, mean);
$dist_normal(seed, mean, deviation);
$dist_poisson(seed, mean);
$dist_t(seed, degree_of_freedom);
$dist_uniform(seed, start, end);

Description:

$random returns a random 32-bit signed integer. Seed controls the numbers that $random returns. The seed must be a reg,integer or time variable.

The $dist_ functions returns pseudo-random values whose characteristics are described by the function name. The seed is an inout parameter and must be an integer.

Example:

A = $random(2);