一、Reset_Delay
module Reset_Delay(iCLK,oRESET);
input iCLK;
output reg oRESET;
reg[19:0] Cont;
always@(posedge iCLK)
begin
if(Cont!=20'hfffff)
begin
Cont<=Cont+1;
oRESET<=1'b0;
end
else
oRESET<=1'b1;
end
endmodule
二、video_sync_generator
module video_sync_generator(
input rst_n,
input vga_clk,
output reg vga_hs,vga_vs,
output reg vga_blank_n,
output valid,
output [10:0] vga_xpos,vga_ypos
);
//Generate the H-Sync & V-Sync
reg[10:0] h_cnt;
reg[10:0] v_cnt;
always@(posedge vga_clk or negedge rst_n)
begin
if(!rst_n)
begin
h_cnt<=11'd0;
v_cnt<=11'd0;
end
else
begin
if(h_cnt==H_TOTAL-1)
begin
h_cnt<=11'd0;
if(v_cnt==V_TOTAL-1)
v_cnt<=11'd0;
else
v_cnt<=v_cnt+11'd1;
end
else
h_cnt<=h_cnt+11'd1;
end
end
wire cHD,cVD,hori_valid,vert_valid,cDEN;
assign cHD=(h_cnt<H_SYNC)?1'b0:1'b1;
assign cVD=(v_cnt<V_SYNC)?1'b0:1'b1;
assign hori_valid=(h_cnt<(H_TOTAL-H_FRONT) && h_cnt>=H_BACK)?1'b1:1'b0;
assign vert_valid=(v_cnt<(V_TOTAL-V_FRONT) && v_cnt>=V_BACK)?1'b1:1'b0;
assign cDEN=hori_valid && vert_valid;
//Delay the iHD,iVD,iDEN for one clock cycle;
always@(negedge vga_clk)
begin
vga_hs<=cHD;
vga_vs<=cVD;
vga_blank_n<=cDEN;
end
//Generate Valid, vga_xpos, vga_ypos
assign valid=(h_cnt>=X_Start && h_cnt<X_Start+H_ACT && v_cnt>=Y_Start && v_cnt<Y_Start+V_ACT)?1'b1:1'b0;
assign vga_xpos=valid?(h_cnt-X_Start):11'b0;
assign vga_ypos=valid?(v_cnt-Y_Start):11'b0;
//-------------------------------------------------------
`define VGA_640_480_60FPS_25MHz
//`define VGA_800_600_72FPS_50MHz
//`define VGA_1024_768_60FPS_65MHz
`ifdef VGA_640_480_60FPS_25MHz
//Horizontal & Vertical Parameter
parameter H_SYNC = 96;
parameter H_BACK = 48;
parameter H_ACT = 640;
parameter H_FRONT= 16;
parameter H_TOTAL= 800;
parameter V_SYNC = 2;
parameter V_BACK = 33;
parameter V_ACT = 480;
parameter V_FRONT= 10;
parameter V_TOTAL= 525;
//Start Offset
parameter X_Start=H_SYNC+H_BACK;
parameter Y_Start= V_SYNC+V_BACK;
`endif
`ifdef VGA_800_600_72FPS_50MHz
//Horizontal & Vertical Parameter
parameter H_SYNC = 120;
parameter H_BACK = 64;
parameter H_ACT = 800;
parameter H_FRONT= 56;
parameter H_TOTAL= 1040;
parameter V_SYNC = 6;
parameter V_BACK = 23;
parameter V_ACT = 600;
parameter V_FRONT= 37;
parameter V_TOTAL= 666;
//Start Offset
parameter X_Start=H_SYNC+H_BACK+H_FRONT;
parameter Y_Start= V_SYNC+V_BACK+V_FRONT;
`endif
`ifdef VGA_1024_768_60FPS_65MHz
//Horizontal & Vertical Parameter
parameter H_SYNC = 136;
parameter H_BACK = 160;
parameter H_ACT = 1024;
parameter H_FRONT= 24;
parameter H_TOTAL= 1344;
parameter V_SYNC = 6;
parameter V_BACK = 29;
parameter V_ACT = 768;
parameter V_FRONT= 3;
parameter V_TOTAL= 806;
//Start Offset
parameter X_Start=H_SYNC+H_BACK+H_FRONT;
parameter Y_Start= V_SYNC+V_BACK+V_FRONT;
`endif
//-------------------------------------------------------
endmodule
三、video_disp_generator
module video_disp_generator
#(
parameter H_ACT = 10'd640,
parameter V_ACT = 10'd480
)
(
input vga_clk,
input rst_n,
input[10:0] vga_xpos,
input[10:0] vga_ypos,
input valid,
output reg[7:0] vga_r,vga_g,vga_b
);
wire[21:0] vga_result=vga_xpos*vga_ypos;
always@(posedge vga_clk or negedge rst_n)
begin
if(!rst_n)
begin
vga_r<=0;
vga_g<=0;
vga_b<=0;
end
else if(valid)
{vga_r,vga_g,vga_b} <= vga_result;
else
{vga_r,vga_g,vga_b} <= 24'h000000;
end
/*
always@(posedge vga_clk or negedge rst_n)
begin
if(!rst_n)
begin
vga_r<=0;
vga_g<=0;
vga_b<=0;
end
else if(valid)
begin
if (vga_xpos >= 0 && vga_xpos < (H_ACT>>3))
{vga_r,vga_g,vga_b} <= 24'hff0000;
else if(vga_xpos >= (H_ACT>>3)*1 && vga_xpos < (H_ACT>>3)*2)
{vga_r,vga_g,vga_b} <= 24'h00ff00;
else if(vga_xpos >= (H_ACT>>3)*2 && vga_xpos < (H_ACT>>3)*3)
{vga_r,vga_g,vga_b} <= 24'h0000ff;
else if(vga_xpos >= (H_ACT>>3)*3 && vga_xpos < (H_ACT>>3)*4)
{vga_r,vga_g,vga_b} <= 24'hffff00;
else if(vga_xpos >= (H_ACT>>3)*4 && vga_xpos < (H_ACT>>3)*5)
{vga_r,vga_g,vga_b} <= 24'h00ffff;
else if(vga_xpos >= (H_ACT>>3)*5 && vga_xpos < (H_ACT>>3)*6)
{vga_r,vga_g,vga_b} <= 24'hff00ff;
else if(vga_xpos >= (H_ACT>>3)*6 && vga_xpos < (H_ACT>>3)*7)
{vga_r,vga_g,vga_b} <= 24'hffffff;
else// if(vga_xpos >= (H_ACT<<3)*7 && vga_xpos < (H_ACT<<3)*8)
{vga_r,vga_g,vga_b} <= 24'hff0000;
end
end
*/
/*
always@(posedge vga_clk or negedge rst_n)
begin
if(!rst_n)
{vga_r,vga_g,vga_b}<=24'b0;
else if(valid)
begin
if((vga_xpos>=0&&vga_xpos<640)&&(vga_ypos>=0&&vga_ypos<80))
{vga_r,vga_g,vga_b}<=24'hff0000;
else if((vga_xpos>=0&&vga_xpos<640)&&(vga_ypos>=0&&vga_ypos<160))
{vga_r,vga_g,vga_b}<=24'h00ff00;
else if((vga_xpos>=0&&vga_xpos<640)&&(vga_ypos>=160&&vga_ypos<240))
{vga_r,vga_g,vga_b}<=24'h0000ff;
else if((vga_xpos>=0&&vga_xpos<640)&&(vga_ypos>=240&&vga_ypos<320))
{vga_r,vga_g,vga_b}<=24'hf0f0f0;
else if((vga_xpos>=0&&vga_xpos<640)&&(vga_ypos>=320&&vga_ypos<400))
{vga_r,vga_g,vga_b}<=24'h0f0f0f;
else if((vga_xpos>=0&&vga_xpos<640)&&(vga_ypos>=400&&vga_ypos<480))
{vga_r,vga_g,vga_b}<=24'hffffff;
else
{vga_r,vga_g,vga_b}<=24'h000000;
end
end
*/
endmodule
四、vga_controller
module vga_controller(
input CLK_50,iRST_N,
//VGA interface
output VGA_HS,VGA_VS,
output VGA_CLK,
output VGA_BLANK_N,
output VGA_SYNC_N,
output[7:0] VGA_R,VGA_G,VGA_B
);
assign VGA_SYNC_N=1'b0; //This pin is unused;
wire DLY_RST;
Reset_Delay r0(
.iCLK(CLK_50),
.oRESET(DLY_RST)
);
pll pll_vga(
.inclk0(CLK_50),
.c0(VGA_CLK)
);
video_sync_generator u1(
.vga_clk(VGA_CLK),
.rst_n(DLY_RST),
.vga_hs(VGA_HS),
.vga_vs(VGA_VS),
.vga_blank_n(VGA_BLANK_N),
.vga_xpos(vga_xpos),
.vga_ypos(vga_ypos),
.valid(valid)
);
wire[10:0] vga_xpos,vga_ypos;
wire valid;
video_disp_generator u2(
.vga_clk(VGA_CLK),
.rst_n(DLY_RST),
.vga_xpos(vga_xpos),
.vga_ypos(vga_ypos),
.valid(valid),
.vga_r(VGA_R),
.vga_g(VGA_G),
.vga_b(VGA_B)
);
endmodule
五、Color Pattern Display