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最新推荐文章于 2024-05-22 17:14:35 发布

Jealky

最新推荐文章于 2024-05-22 17:14:35 发布

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分类专栏： FPGA 文章标签： fpga开发

本文链接：https://blog.csdn.net/weixin_45074094/article/details/124450918

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本设计为VGA接口的verilog驱动实现程序，设计以800*600像素为例显示一个静态图形：边框宽度为20像素的矩形边框和宽度为30像素的正方形区域。

module vga(
    clk, rst_n, hsync, vsync, vga_r, vga_g, vga_b
);

input   clk;
input   rst_n;
output  hsync;
output  vsync;
output  vga_r;
output  vga_g;
output  vga_b;

reg[11:0]   x_cnt;
reg[11:0]   y_cnt;
//-----------------------------------------------
//120+64+800+56 = 1040
//------------------------------------------------
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        x_cnt <= 0;
    else if(x_cnt == 11'd1040-1)
            x_cnt <= 0;
         else
            x_cnt <= x_cnt + 1'b1;
end

//-------------------------------------------------
//6+23+600+37= 666
//------------------------------------------------
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        y_cnt <= 0;
    else if((y_cnt == 10'd666-1) && (x_cnt == 11'd1040-1))
            y_cnt <= 0;
         else if(x_cnt == 11'd1040-1)
                y_cnt <= y_cnt + 1'b1;
end

//--------------------------------------------------------
//x[184, 983]  y[29, 628]
//--------------------------------------------------------
wire        valid;
wire[9:0]   xpos, ypos;

assign valid = (x_cnt > 11'd183) && (x_cnt < 984) && (y_cnt > 10'd28) && (y_cnt < 10'd629);
assign xpos = x_cnt - 11'd183;
assign ypos = y_cnt - 10'd28;

//-----------------------------------------------------
//hsync,  vsync
//-----------------------------------------------------
reg hsync, vsync;

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        hsync <= 1'b0;
    else if(x_cnt == 11'd1039)
            hsync <= 1'b0;
         else if(x_cnt == 11'd119)
                hsync <= 1'b1;
end
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        vsync <= 1'b0;
    else if((y_cnt == 11'd665) && (x_cnt == 11'd1039))
            vsync <= 1'b0;
         else if((y_cnt == 11'd5) && (x_cnt == 11'd1039))
                vsync <= 1'b1;
end

//------------------------------------------------------
//-----------------------------------------------------
wire a_dis, b_dis, c_dis, d_dis;

assign a_dis = (xpos >= 200) && (xpos <= 220) && (ypos >= 140) && (ypos <= 460);
assign b_dis = (xpos >= 580) && (xpos <= 600) && (ypos >= 140) && (ypos <= 460);
assign c_dis = (xpos >= 220) && (xpos <= 580) && (ypos >= 140) && (ypos <= 160);
assign d_dis = (xpos >= 220) && (xpos <= 580) && (ypos >= 440) && (ypos <= 460);

//---------------------------------------------------------------
//-----------------------------------------------------------------
wire e_rdy;

assign e_rdy = (xpos >= 385) && (xpos <= 415) && (ypos >= 285) && (ypos <= 315);

//-------------------------------------------------------------------------
//------------------------------------------------------------------------
assign vga_r = valid ? e_rdy : 1'b0;
assign vga_g = valid ? (a_dis || b_dis || c_dis || d_dis) : 1'b0;
assign vga_b = valid ? ~(a_dis || b_dis || c_dis || d_dis) : 1'b0;

endmodule